Volume 25,
Number 1,
January 2006
- Görschwin Fey, Rolf Drechsler:
Minimizing the number of paths in BDDs: Theory and algorithm.
4-11
Electronic Edition (link) BibTeX
- Wenjian Yu, Mengsheng Zhang, Zeyi Wang:
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.
12-18
Electronic Edition (link) BibTeX
- Kyosun Kim, Ramesh Karri, Miodrag Potkonjak:
Micropreemption synthesis: an enabling mechanism for multitask VLSI systems.
19-30
Electronic Edition (link) BibTeX
- María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Bitwise scheduling to balance the computational cost of behavioral specifications.
31-46
Electronic Edition (link) BibTeX
- Jaewon Seo, Taewhan Kim, Joonwon Lee:
Optimal intratask dynamic voltage-scaling technique and its practical extensions.
47-57
Electronic Edition (link) BibTeX
- Arijit Raychowdhury, Kaushik Roy:
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
58-65
Electronic Edition (link) BibTeX
- Jaijeet S. Roychowdhury, Robert C. Melville:
Delivering global DC convergence for large mixed-signal circuits via homotopy/continuation methods.
66-78
Electronic Edition (link) BibTeX
- Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee:
Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications.
79-91
Electronic Edition (link) BibTeX
- Li Shang, Li-Shiuan Peh, Niraj K. Jha:
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks.
92-110
Electronic Edition (link) BibTeX
- Ying Zhang, Krishnendu Chakrabarty:
A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems.
111-125
Electronic Edition (link) BibTeX
- Imad A. Ferzli, Farid N. Najm:
Analysis and verification of power grids considering process-induced leakage-current variations.
126-143
Electronic Edition (link) BibTeX
- Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power-supply pads and pins.
144-154
Electronic Edition (link) BibTeX
- Quming Zhou, Kartik Mohanram:
Gate sizing to radiation harden combinational logic.
155-166
Electronic Edition (link) BibTeX
- Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov:
Fast detection of data retention faults and other SRAM cell open defects.
167-180
Electronic Edition (link) BibTeX
- Qiang Xu, Nicola Nicolici:
Multifrequency TAM design for hierarchical SOCs.
181-196
Electronic Edition (link) BibTeX
- Shih-yu Yang, Christos A. Papachristou:
A method for detecting interconnect DSM defects in systems on chip.
197-204
Electronic Edition (link) BibTeX
Volume 25,
Number 2,
February 2006
- Fei Su, Krishnendu Chakrabarty, Richard B. Fair:
Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges.
211-223
Electronic Edition (link) BibTeX
- Jun Zeng:
Modeling and Simulation of Electrified Droplets and Its Application to Computer-Aided Design of Digital Microfluidics.
224-233
Electronic Edition (link) BibTeX
- Jan Lienemann, Andreas Greiner, Jan G. Korvink:
Modeling, Simulation, and Optimization of Electrowetting.
234-247
Electronic Edition (link) BibTeX
- Xin Wang, Joe Kanapka, Wenjing Ye, Narayan R. Aluru, Jacob White:
Algorithms in FastStokes and Its Application to Micromachined Device Simulation.
248-257
Electronic Edition (link) BibTeX
- Yi Wang, Qiao Lin, Tamal Mukherjee:
Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic Lab-on-a-Chip Systems.
258-273
Electronic Edition (link) BibTeX
- Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White:
FFTSVD: A Fast Multiscale Boundary-Element Method Solver Suitable for Bio-MEMS and Biomolecule Simulation.
274-284
Electronic Edition (link) BibTeX
- Dmitry Vasilyev, Michal Rewienski, Jacob White:
Macromodel Generation for BioMEMS Components Using a Stabilized Balanced Truncation Plus Trajectory Piecewise-Linear Approach.
285-293
Electronic Edition (link) BibTeX
- Anand S. Bedekar, Yi Wang, S. Krishnamoorthy, Sachin S. Siddhaye, Shankar Sundaram:
System-Level Simulation of Flow-Induced Dispersion in Lab-on-a-Chip Systems.
294-304
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Computer-Aided Optimization of DNA Array Design and Manufacturing.
305-320
Electronic Edition (link) BibTeX
- Anton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan:
Synthesis of Multiplexed Biofluidic Microchips.
321-333
Electronic Edition (link) BibTeX
- Karl-Friedrich Böhringer:
Modeling and Controlling Parallel Tasks in Droplet-Based Microfluidic Systems.
334-344
Electronic Edition (link) BibTeX
- Eric J. Griffith, Srinivas Akella, Mark K. Goldberg:
Performance Characterization of a Reconfigurable Planar-Array Digital Microfluidic System.
345-357
Electronic Edition (link) BibTeX
- Sungroh Yoon, Luca Benini, Giovanni De Micheli:
A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis.
358-377
Electronic Edition (link) BibTeX
- Ryan Magargle, James F. Hoburg, Tamal Mukherjee:
Microfluidic Injector Models Based on Artificial Neural Networks.
378-385
Electronic Edition (link) BibTeX
Volume 25,
Number 3,
March 2006
- Sangyun Kim, Peter A. Beerel:
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.
389-402
Electronic Edition (link) BibTeX
- Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda:
Verification of timed circuits with failure-directed abstractions.
403-412
Electronic Edition (link) BibTeX
- Kaijie Wu, Ramesh Karri:
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique.
413-422
Electronic Edition (link) BibTeX
- Jason Helge Anderson, Farid N. Najm:
Active leakage power optimization for FPGAs.
423-437
Electronic Edition (link) BibTeX
- Dongkun Shin, Jihong Kim:
Dynamic voltage scaling of mixed task sets in priority-driven systems.
438-453
Electronic Edition (link) BibTeX
- Hongmei Li, Cole E. Zemke, Giorgos Manetas, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris:
An automated and efficient substrate noise analysis tool.
454-468
Electronic Edition (link) BibTeX
- Ruibing Lu, Cheng-Kok Koh:
Performance analysis of latency-insensitive systems.
469-483
Electronic Edition (link) BibTeX
- Zhuo Li, Weiping Shi:
An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types.
484-489
Electronic Edition (link) BibTeX
- Muhammet Mustafa Ozdal, Martin D. F. Wong:
Algorithmic study of single-layer bus routing for high-speed boards.
490-503
Electronic Edition (link) BibTeX
- Navaratnasothie Selvakkumaran, George Karypis:
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization.
504-517
Electronic Edition (link) BibTeX
- Akshay Sharma, Carl Ebeling, Scott Hauck:
PipeRoute: a pipelining-aware router for reconfigurable architectures.
518-532
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Sherief Reda:
New and improved BIST diagnosis methods from combinatorial Group testing theory.
533-543
Electronic Edition (link) BibTeX
- Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.
544-557
Electronic Edition (link) BibTeX
- Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis.
558-575
Electronic Edition (link) BibTeX
- Joonhwan Yi, John P. Hayes:
High-level delay test generation for modular circuits.
576-590
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.
591-596
Electronic Edition (link) BibTeX
- Hua Tang, Alex Doboli:
High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption.
597-607
Electronic Edition (link) BibTeX
Volume 25,
Number 4,
April 2006
- Qinghua Liu, Malgorzata Marek-Sadowska:
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.
611-624
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- Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar:
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.
625-636
Electronic Edition (link) BibTeX
- Tung-Chieh Chen, Yao-Wen Chang:
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.
637-650
Electronic Edition (link) BibTeX
- Baris Taskin, Ivan S. Kourtev:
Delay Insertion Method in Clock Skew Scheduling.
651-663
Electronic Edition (link) BibTeX
- Jaskirat Singh, Sachin S. Sapatnekar:
Partition-Based Algorithm for Power Grid Design Using Locality.
664-677
Electronic Edition (link) BibTeX
- Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm.
678-691
Electronic Edition (link) BibTeX
- Brent Goplen, Sachin S. Sapatnekar:
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives.
692-709
Electronic Edition (link) BibTeX
- James D. Ma, Rob A. Rutenbar:
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.
710-724
Electronic Edition (link) BibTeX
- Yukiko Kubo, Atsushi Takahashi:
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.
725-733
Electronic Edition (link) BibTeX
- Di Wu, Jiang Hu, Rabi N. Mahapatra:
Antenna Avoidance in Layer Assignment.
734-738
Electronic Edition (link) BibTeX
Volume 25,
Number 5,
May 2006
- Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks.
743-755
Electronic Edition (link) BibTeX
- Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein:
Hardware compilation of application-specific memory-access interconnect.
756-771
Electronic Edition (link) BibTeX
- Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh:
Optimal register sharing for high-level synthesis of SSA form programs.
772-779
Electronic Edition (link) BibTeX
- Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain:
On partitioning and symbolic model checking.
780-788
Electronic Edition (link) BibTeX
- T. Sasao:
Analysis and synthesis of weighted-sum functions.
789-796
Electronic Edition (link) BibTeX
- Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias:
Comparison of two designs for the multifunction vehicle bus.
797-805
Electronic Edition (link) BibTeX
- Ying Yi, Roger Woods:
Hierarchical synthesis of complex DSP functions using IRIS.
806-820
Electronic Edition (link) BibTeX
- Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses.
821-836
Electronic Edition (link) BibTeX
- Srinivas Bodapati, Farid N. Najm:
High-level current macro model for logic blocks.
837-855
Electronic Edition (link) BibTeX
- Yan Feng, Dinesh P. Mehta:
Module relocation to obtain feasible constrained floorplans.
856-866
Electronic Edition (link) BibTeX
- Premachandran R. Menon, Weifeng Xu, Russell Tessier:
Design-specific path delay testing in lookup-table-based FPGAs.
867-877
Electronic Edition (link) BibTeX
- Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Concurrent detection of erroneous responses in linear analog circuits.
878-891
Electronic Edition (link) BibTeX
- Kanak Agarwal, Dennis Sylvester, David Blaauw:
Modeling and analysis of crosstalk noise in coupled RLC interconnects.
892-901
Electronic Edition (link) BibTeX
- Rüdiger Ebendt, Rolf Drechsler:
Effect of improved lower bounds in dynamic BDD reordering.
902-909
Electronic Edition (link) BibTeX
- Kooho Jung, William R. Eisenstadt, Robert M. Fox:
SPICE-based mixed-mode S-parameter calculations for four-port and three-port circuits.
909-913
Electronic Edition (link) BibTeX
- Hong-Sik Kim, Sungho Kang:
Increasing encoding efficiency of LFSR reseeding-based test compression.
913-917
Electronic Edition (link) BibTeX
- Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need?
917-924
Electronic Edition (link) BibTeX
- Ewout Martens, Georges G. E. Gielen:
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models.
924-932
Electronic Edition (link) BibTeX
- Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs.
932-938
Electronic Edition (link) BibTeX
Volume 25,
Number 6,
June 2006
- Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi:
Multilevel symmetry-constraint generation for retargeting large analog layouts.
945-960
Electronic Edition (link) BibTeX
- Shih-Hsu Huang, Yow-Tyng Nieh:
Synthesis of nonzero clock skew circuits.
961-976
Electronic Edition (link) BibTeX
- Alan Mishchenko, Robert K. Brayton:
A theory of nondeterministic networks.
977-999
Electronic Edition (link) BibTeX
- Vivek V. Shende, Stephen S. Bullock, Igor L. Markov:
Synthesis of quantum-logic circuits.
1000-1010
Electronic Edition (link) BibTeX
- Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Linear cofactor relationships in Boolean functions.
1011-1023
Electronic Edition (link) BibTeX
- Ravindra Jejurikar, Rajesh K. Gupta:
Energy-aware task scheduling with task synchronization for embedded real-time systems.
1024-1037
Electronic Edition (link) BibTeX
- Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda:
Impact of stress-induced backflow on full-chip electromigration risk assessment.
1038-1046
Electronic Edition (link) BibTeX
- Junjun Li, S. Joshi, R. Barnes, E. Rosenbaum:
Compact modeling of on-chip ESD protection devices using Verilog-A.
1047-1063
Electronic Edition (link) BibTeX
- Debjit Sinha, Hai Zhou:
Gate-size optimization under timing constraints for coupling-noise reduction.
1064-1074
Electronic Edition (link) BibTeX
- Peter G. Sassone, Sung Kyu Lim:
Traffic: a novel geometric algorithm for fast wire-optimized floorplanning.
1075-1086
Electronic Edition (link) BibTeX
- Zhao Li, C.-J. Richard Shi:
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.
1087-1103
Electronic Edition (link) BibTeX
- Tao Jiang, R. D. (Shawn) Blanton:
Inductive fault analysis of surface-micromachined MEMS.
1104-1116
Electronic Edition (link) BibTeX
- Manan Syal, Michael S. Hsiao:
New techniques for untestable fault identification in sequential circuits.
1117-1131
Electronic Edition (link) BibTeX
- Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
Three-dimensional place and route for FPGAs.
1132-1140
Electronic Edition (link) BibTeX
- Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
1140-1145
Electronic Edition (link) BibTeX
- Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
1146-1154
Electronic Edition (link) BibTeX
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis:
A high-performance data path for synthesizing DSP kernels.
1154-1162
Electronic Edition (link) BibTeX
- Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri:
Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design.
1163-1169
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.
1170-1175
Electronic Edition (link) BibTeX
- Anand Rajaram, Jiang Hu, Rabi N. Mahapatra:
Reducing clock skew variability via crosslinks.
1176-1182
Electronic Edition (link) BibTeX
- Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model.
1183-1191
Electronic Edition (link) BibTeX
Volume 25,
Number 7,
July 2006
- Kris Tiri, Ingrid Verbauwhede:
A digital design flow for secure integrated circuits.
1197-1208
Electronic Edition (link) BibTeX
- Laura Pozzi, Kubilay Atasu, Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets.
1209-1229
Electronic Edition (link) BibTeX
- Christopher Umans, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
Complexity of two-level logic minimization.
1230-1246
Electronic Edition (link) BibTeX
- Jongsun Park, Khurram Muhammad, Kaushik Roy:
Efficient modeling of 1/falpha/ noise using multirate process.
1247-1256
Electronic Edition (link) BibTeX
- Guoyong Shi, Bo Hu, C.-J. Richard Shi:
On symbolic model order reduction.
1257-1272
Electronic Edition (link) BibTeX
- Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw:
Statistical interconnect metrics for physical-design optimization.
1273-1288
Electronic Edition (link) BibTeX
- Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim:
Profile-guided microarchitectural floor planning for deep submicron processor design.
1289-1300
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Sherief Reda:
Wirelength minimization for min-cut placements via placement feedback.
1301-1312
Electronic Edition (link) BibTeX
- Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov:
Min-cut floorplacement.
1313-1326
Electronic Edition (link) BibTeX
- Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak:
A statistical methodology for wire-length prediction.
1327-1336
Electronic Edition (link) BibTeX
- Peng Rong, Massoud Pedram:
Battery-aware power management based on Markovian decision processes.
1337-1349
Electronic Edition (link) BibTeX
- Munkang Choi, Linda S. Milor:
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.
1350-1367
Electronic Edition (link) BibTeX
- Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury:
An integrated DFT solution for mixed-signal SOCs.
1368-1377
Electronic Edition (link) BibTeX
- L. Knockaert, T. Dhaene:
Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models.
1377-1381
Electronic Edition (link) BibTeX
- Knockaert Radecka, Zeljko Zilic:
Arithmetic transforms for compositions of sequential and imprecise datapaths.
1382-1391
Electronic Edition (link) BibTeX
- C.-J. Richard Shi, Michael W. Tian, Guoyong Shi:
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.
1392-1400
Electronic Edition (link) BibTeX
- Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen:
Analytical model for crosstalk and intersymbol interference in point-to-point buses.
1400-1410
Electronic Edition (link) BibTeX
- Dan Zhao, Shambhu J. Upadhyaya, Martin Margala:
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip.
1411-1418
Electronic Edition (link) BibTeX
Volume 25,
Number 8,
August 2006
- Hua Tang, Hui Zhang, Alex Doboli:
Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling.
1421-1440
Electronic Edition (link) BibTeX
- Behzad Akbarpour, Sofiène Tahar:
An approach for the formal verification of DSP designs using Theorem proving.
1441-1457
Electronic Edition (link) BibTeX
- Hiren D. Patel, Deepak Mathaikutty, David Berner, Sandeep K. Shukla:
CARH: service-oriented architecture for validating system-level designs.
1458-1474
Electronic Edition (link) BibTeX
- Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Gate-length biasing for runtime-leakage control.
1475-1485
Electronic Edition (link) BibTeX
- Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
1486-1495
Electronic Edition (link) BibTeX
- Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He:
Wideband passive multiport model order reduction and realization of RLCM circuits.
1496-1509
Electronic Edition (link) BibTeX
- Muhammet Mustafa Ozdal, Martin D. F. Wong:
Algorithms for simultaneous escape routing and Layer assignment of dense PCBs.
1510-1522
Electronic Edition (link) BibTeX
- P. Kannan, D. Bhatia:
Interconnect estimation for FPGAs.
1523-1534
Electronic Edition (link) BibTeX
- Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
Pseudofunctional testing.
1535-1546
Electronic Edition (link) BibTeX
- Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris:
Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines.
1547-1554
Electronic Edition (link) BibTeX
- Seongmoon Wang, Srimat T. Chakradhar:
A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.
1555-1564
Electronic Edition (link) BibTeX
- Seongmoon Wang, Sandeep K. Gupta:
LT-RTPG: a new test-per-scan BIST TPG for low switching activity.
1565-1574
Electronic Edition (link) BibTeX
Volume 25,
Number 9,
September 2006
- Chuan Lin, Hai Zhou:
Optimal wire retiming without binary search.
1577-1588
Electronic Edition (link) BibTeX
- Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Application-specific heterogeneous multiprocessor synthesis using extensible processors.
1589-1602
Electronic Edition (link) BibTeX
- Oskar Mencer:
ASC: a stream compiler for computing with FPGAs.
1603-1617
Electronic Edition (link) BibTeX
- Bin Wu, Jianwen Zhu, Farid N. Najm:
Dynamic-range estimation.
1618-1636
Electronic Edition (link) BibTeX
- Josep Carmona, José Manuel Colom, Jordi Cortadella, F. García-Vallés:
Synthesis of asynchronous controllers using integer linear programming.
1637-1651
Electronic Edition (link) BibTeX
- William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski:
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.
1652-1663
Electronic Edition (link) BibTeX
- Jun Chen, Lei He:
Modeling and synthesis of multiport transmission line for multichannel communication.
1664-1676
Electronic Edition (link) BibTeX
- B. Lasbouygues, S. Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Logical effort model extension to propagation delay representation.
1677-1684
Electronic Edition (link) BibTeX
- Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester:
Analytical yield prediction considering leakage/performance correlation.
1685-1695
Electronic Edition (link) BibTeX
- Xiangyin Zeng, Jiangqi He, M. N. Abdulla, Qing-Lun Chen:
Understanding and closed-form-formula determination of frequency-dependent bonding-pad characterization.
1696-1704
Electronic Edition (link) BibTeX
- Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann:
Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.
1705-1718
Electronic Edition (link) BibTeX
- Jason Cong, Michail Romesis, Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning.
1719-1732
Electronic Edition (link) BibTeX
- Prashant Saxena:
On controlling perturbation due to repeaters during quadratic placement.
1733-1743
Electronic Edition (link) BibTeX
- Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong:
Minimizing wire length in floorplanning.
1744-1753
Electronic Edition (link) BibTeX
- Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
An ECO routing algorithm for eliminating coupling-capacitance violations.
1754-1762
Electronic Edition (link) BibTeX
- Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra:
IC thermal simulation and modeling via efficient multigrid-based approaches.
1763-1776
Electronic Edition (link) BibTeX
- Hao Gang Wang, Chi Hou Chan, Leung Tsang, Vikram Jandhyala:
On sampling algorithms in multilevel QR factorization method for magnetoquasistatic analysis of integrated circuits over multilayered lossy substrates.
1777-1792
Electronic Edition (link) BibTeX
- Arijit Mondal, P. P. Chakrabarti:
Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic.
1793-1814
Electronic Edition (link) BibTeX
- Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein:
Timing analysis for full-custom circuits using symbolic DC formulations.
1815-1830
Electronic Edition (link) BibTeX
- Xiaohua Kong, Radu Negulescu:
Semihiding operators and active-edge specification.
1831-1846
Electronic Edition (link) BibTeX
- Ruiming Chen, Hai Zhou:
Statistical timing verification for transparently latched circuits.
1847-1855
Electronic Edition (link) BibTeX
- Victor De La Luz, Mahmut T. Kandemir, Ibrahim Kolcu:
Reducing memory energy consumption of embedded applications that process dynamically allocated data.
1855-1860
Electronic Edition (link) BibTeX
- Ruifeng Guo, Srikanth Venkataraman:
An algorithmic technique for diagnosis of faulty scan chains.
1861-1868
Electronic Edition (link) BibTeX
- Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo:
Analytical bound for unwanted clock skew due to wire width variation.
1869-1876
Electronic Edition (link) BibTeX
- Jens Vygen:
Slack in static timing analysis.
1876-1885
Electronic Edition (link) BibTeX
Volume 25,
Number 10,
October 2006
- Lihong Zhang, Rabin Raut, Yingtao Jiang, Ulrich Kleine:
Placement Algorithm in Analog-Layout Designs.
1889-1903
Electronic Edition (link) BibTeX
- Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou:
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.
1904-1921
Electronic Edition (link) BibTeX
- Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni:
Design-Intent Coverage - A New Paradigm for Formal Property Verification.
1922-1934
Electronic Edition (link) BibTeX
- J.-G. Lee, C.-M. Kyung:
PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation.
1935-1949
Electronic Edition (link) BibTeX
- Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet:
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.
1950-1968
Electronic Edition (link) BibTeX
- Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Use of Computation-Unit Integrated Memories in High-Level Synthesis.
1969-1989
Electronic Edition (link) BibTeX
- Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides:
Accuracy-Guaranteed Bit-Width Optimization.
1990-2000
Electronic Edition (link) BibTeX
- Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta:
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.
2001-2011
Electronic Edition (link) BibTeX
- Anup Hosangadi, Farzan Fallah, Ryan Kastner:
Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination.
2012-2022
Electronic Edition (link) BibTeX
- Yan Lin, Lei He:
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.
2023-2034
Electronic Edition (link) BibTeX
- Manish Verma, Lars Wehmeyer, Peter Marwedel:
Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems.
2035-2051
Electronic Edition (link) BibTeX
- Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Leakage Currents in Double-Gate Technologies.
2052-2061
Electronic Edition (link) BibTeX
- N. Wong, V. Balakrishnan, C.-K. Koh, T.-S. Ng:
Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction.
2062-2075
Electronic Edition (link) BibTeX
- Andrew A. Kennings, Kristofer Vorwerk:
Force-Directed Methods for Generic Placement.
2076-2087
Electronic Edition (link) BibTeX
- Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh:
Statistical Analysis and Design of HARP FPGAs.
2088-2102
Electronic Edition (link) BibTeX
- Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
RTL-Aware Cycle-Accurate Functional Power Estimation.
2103-2117
Electronic Edition (link) BibTeX
- J. Cervenka, W. Wessner, E. Al-Ani, Tibor Grasser, Siegfried Selberherr:
Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential Equations.
2118-2128
Electronic Edition (link) BibTeX
- W. Wessner, J. Cervenka, Clemens Heitzinger, Andreas Hössinger, Siegfried Selberherr:
Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing Processes.
2129-2139
Electronic Edition (link) BibTeX
- Ming Zhang, Naresh R. Shanbhag:
Soft-Error-Rate-Analysis (SERA) Methodology.
2140-2155
Electronic Edition (link) BibTeX
- Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm:
Voltage-Aware Static Timing Analysis.
2156-2169
Electronic Edition (link) BibTeX
- Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett:
First-Order Incremental Block-Based Statistical Timing Analysis.
2170-2180
Electronic Edition (link) BibTeX
- Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Simulating Resistive-Bridging and Stuck-At Faults.
2181-2192
Electronic Edition (link) BibTeX
- Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
2193-2206
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Generation of Functional Broadside Tests for Transition Faults.
2207-2218
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.
2219-2227
Electronic Edition (link) BibTeX
- Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie:
A Metric for Automatic Word-Length Determination of Hardware Datapaths.
2228-2231
Electronic Edition (link) BibTeX
- M. Capobianchi, V. Labay, F. Shi, G. Mizushima:
Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions.
2231-2241
Electronic Edition (link) BibTeX
- Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Testability of SPP Three-Level Logic Networks in Static Fault Models.
2241-2248
Electronic Edition (link) BibTeX
- Jacob R. Minz, Sung Kyu Lim:
Block-level 3-D Global Routing With an Application to 3-D Packaging.
2248-2257
Electronic Edition (link) BibTeX
- S.-W. Tu, Y.-W. Chang, J.-Y. Jou:
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.
2258-2264
Electronic Edition (link) BibTeX
- Janet Meiling Wang, Jun Li, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla:
Modeling the Driver Load in the Presence of Process Variations.
2264-2275
Electronic Edition (link) BibTeX
- Qingwei Wu, Michael S. Hsiao:
State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation.
2275-2282
Electronic Edition (link) BibTeX
- Shu Yan, Vivek Sarin, Weiping Shi:
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction.
2282-2286
Electronic Edition (link) BibTeX
- Bo Yang, Kaijie Wu, Ramesh Karri:
Secure Scan: A Design-for-Test Architecture for Crypto Chips.
2287-2293
Electronic Edition (link) BibTeX
Volume 25,
Number 11,
November 2006
- Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi:
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement.
2297-2316
Electronic Edition (link) BibTeX
- Pallav Gupta, Abhinav Agrawal, Niraj K. Jha:
An Algorithm for Synthesis of Reversible Logic Circuits.
2317-2330
Electronic Edition (link) BibTeX
- Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.
2331-2340
Electronic Edition (link) BibTeX
- C.-T. Hsieh, J.-C. Lin, S.-C. Chang:
Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits.
2341-2352
Electronic Edition (link) BibTeX
- Nikolay Rubanov:
A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization.
2353-2363
Electronic Edition (link) BibTeX
- Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh:
A Unified Theory of Timing Budget Management.
2364-2375
Electronic Edition (link) BibTeX
- Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah:
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.
2376-2392
Electronic Edition (link) BibTeX
- W.-K. Mak, C.-L. Lai:
On Constrained Pin-Mapping for FPGA-PCB Codesign.
2393-2401
Electronic Edition (link) BibTeX
- Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
2402-2412
Electronic Edition (link) BibTeX
- Paolo Maffezzoni, Lorenzo Codecasa, Dario D'Amore:
Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits.
2413-2426
Electronic Edition (link) BibTeX
- Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
2427-2436
Electronic Edition (link) BibTeX
- Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen:
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables.
2437-2449
Electronic Edition (link) BibTeX
- Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni:
Defect Modeling Using Fault Tuples.
2450-2464
Electronic Edition (link) BibTeX
- Érika F. Cota, Chunsheng Liu:
Constraint-Driven Test Scheduling for NoC-Based Systems.
2465-2478
Electronic Edition (link) BibTeX
- Petros Oikonomakos, Mark Zwolinski:
An Integrated High-Level On-Line Test Synthesis Tool.
2479-2491
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Improved n-Detection Test Sequences Under Transparent Scan.
2492-2501
Electronic Edition (link) BibTeX
- Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.
2502-2512
Electronic Edition (link) BibTeX
- Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen:
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.
2513-2525
Electronic Edition (link) BibTeX
- Liang Zhang, Indradeep Ghosh, Michael S. Hsiao:
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.
2526-2538
Electronic Edition (link) BibTeX
- Milos Hrkic, John Lillis, Giancarlo Beraudo:
An Approach to Placement-Coupled Logic Replication.
2539-2551
Electronic Edition (link) BibTeX
- Hung-Ming Chen, I-Min Liu, Martin D. F. Wong:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
2552-2556
Electronic Edition (link) BibTeX
- Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.
2556-2564
Electronic Edition (link) BibTeX
- Feng Gao, John P. Hayes:
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction.
2564-2571
Electronic Edition (link) BibTeX
- Yutao Hu, Kartikeya Mayaram:
Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation.
2571-2578
Electronic Edition (link) BibTeX
- Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos:
On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG.
2578-2586
Electronic Edition (link) BibTeX
- N.-C. Lai, S.-J. Wang, Y.-H. Fu:
Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.
2586-2594
Electronic Edition (link) BibTeX
- Fang Liu, Sule Ozev, Martin A. Brooke:
Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements.
2594-2605
Electronic Edition (link) BibTeX
- P. Min, H. Yi, J. Song, S. Baeg, S. Park:
Efficient Interconnect Test Patterns for Crosstalk and Static Faults.
2605-2608
Electronic Edition (link) BibTeX
Volume 25,
Number 12,
December 2006
- Arthur Nieuwoudt, Yehia Massoud:
Variability-Aware Multilevel Integrated Spiral Inductor Synthesis.
2613-2625
Electronic Edition (link) BibTeX
- Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino:
Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.
2626-2637
Electronic Edition (link) BibTeX
- Natasa Miskov-Zivanov, Diana Marculescu:
Circuit Reliability Analysis Using Symbolic Techniques.
2638-2649
Electronic Edition (link) BibTeX
- Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha:
Design Exploration With Imprecise Latency and Register Constraints.
2650-2662
Electronic Edition (link) BibTeX
- Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak:
Latency-Guided On-Chip Bus-Network Design.
2663-2673
Electronic Edition (link) BibTeX
- Jie-Hong Roland Jiang, Robert K. Brayton:
Retiming and Resynthesis: A Complexity Perspective.
2674-2686
Electronic Edition (link) BibTeX
- Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong:
Protecting Combinational Logic Synthesis Solutions.
2687-2696
Electronic Edition (link) BibTeX
- Le Cai, Nathaniel Pettis, Yung-Hsiang Lu:
Joint Power Management of Memory and Disk Under Performance Constraints.
2697-2711
Electronic Edition (link) BibTeX
- Ali Iranli, Massoud Pedram:
Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines.
2712-2725
Electronic Edition (link) BibTeX
- Yuantao Peng, Xun Liu:
An Efficient Low-Power Repeater-Insertion Scheme.
2726-2736
Electronic Edition (link) BibTeX
- Ravishankar Rao, Sarma B. K. Vrudhula:
Energy-Optimal Speed Control of a Generic Device.
2737-2746
Electronic Edition (link) BibTeX
- Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu:
Wafer Topography-Aware Optical Proximity Correction.
2747-2756
Electronic Edition (link) BibTeX
- Hessa Al-Junaid, Tom J. Kazmierski, Peter R. Wilson, Jerzy Baranowski:
Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis.
2757-2764
Electronic Edition (link) BibTeX
- Aditya Bansal, Bipul Chandra Paul, Kaushik Roy:
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.
2765-2774
Electronic Edition (link) BibTeX
- Luis Miguel Silveira, Joel R. Phillips:
Resampling Plans for Sample Point Selection in Multipoint Model-Order Reduction.
2775-2783
Electronic Edition (link) BibTeX
- Muhammet Mustafa Ozdal, Martin D. F. Wong:
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards.
2784-2794
Electronic Edition (link) BibTeX
- Lei Cheng, Martin D. F. Wong:
Floorplan Design for Multimillion Gate FPGAs.
2795-2805
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Sherief Reda:
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.
2806-2819
Electronic Edition (link) BibTeX
- Kaviraj Chopra, Sarma B. K. Vrudhula:
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States.
2820-2832
Electronic Edition (link) BibTeX
- Xiaochun Duan, Kartikeya Mayaram:
Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method.
2833-2842
Electronic Edition (link) BibTeX
- Xiaochun Duan, Kartikeya Mayaram:
Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method.
2843-2851
Electronic Edition (link) BibTeX
- Peng Li:
Statistical Sampling-Based Parametric Analysis of Power Grids.
2852-2867
Electronic Edition (link) BibTeX
- Zhao Li, C.-J. Richard Shi:
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.
2868-2881
Electronic Edition (link) BibTeX
- Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang:
Fast Thermal Simulation for Runtime Temperature Tracking and Management.
2882-2893
Electronic Edition (link) BibTeX
- Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing Structural Bias in Technology Mapping.
2894-2903
Electronic Edition (link) BibTeX
- Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt:
Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.
2904-2918
Electronic Edition (link) BibTeX
- Jingcao Hu, Ümit Y. Ogras, Radu Marculescu:
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design.
2919-2933
Electronic Edition (link) BibTeX
- Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
2934-2943
Electronic Edition (link) BibTeX
- Fei Su, Krishnendu Chakrabarty:
Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips.
2944-2953
Electronic Edition (link) BibTeX
- Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
2954-2964
Electronic Edition (link) BibTeX
- Debjit Sinha, Hai Zhou:
Statistical Timing Analysis With Coupling.
2965-2975
Electronic Edition (link) BibTeX
- Wei-Shen Wang, Michael Orshansky:
Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation.
2976-2988
Electronic Edition (link) BibTeX
- Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi:
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.
2989-2996
Electronic Edition (link) BibTeX
- Mario R. Casu, Luca Macchiarulo:
Floorplanning With Wire Pipelining in Adaptive Communication Channels.
2996-3004
Electronic Edition (link) BibTeX
- Ruiming Chen, Hai Zhou:
An Efficient Data Structure for Maxplus Merge in Dynamic Programming.
3004-3009
Electronic Edition (link) BibTeX
- Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava:
Probabilistic Evaluation of Solutions in Variability-Driven Optimization.
3010-3016
Electronic Edition (link) BibTeX
- Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim:
Profile-Driven Instruction Mapping for Dataflow Architectures.
3017-3025
Electronic Edition (link) BibTeX
- Stelios Neophytou, Maria K. Michael, Spyros Tragoudas:
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.
3026-3035
Electronic Edition (link) BibTeX
- Xiren Wang, Wenjian Yu, Zeyi Wang:
Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile.
3035-3042
Electronic Edition (link) BibTeX
- Hong Li, Wen-Yan Yin, Junfa Mao:
Comments on "Modeling of Metallic Carbon-Nanotube Interconnects for Circuit Simulations and a Comparison With Cu Interconnects for Sealed Technologies".
3042-3044
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:16 2009
by Michael Ley (ley@uni-trier.de)