| 2007 |
|---|
| 9 | EE | Yu-Shen Yang,
Subarnarekha Sinha,
Andreas G. Veneris,
Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs.
ASP-DAC 2007: 402-407 |
| 2006 |
|---|
| 8 | EE | Alan Mishchenko,
Jin S. Zhang,
Subarnarekha Sinha,
Jerry R. Burch,
Robert K. Brayton,
Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 743-755 (2006) |
| 2004 |
|---|
| 7 | EE | Sunil P. Khatri,
Subarnarekha Sinha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
SPFD-based wire removal in standard-cell and network-of-PLA circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004) |
| 2002 |
|---|
| 6 | EE | Subarnarekha Sinha,
Alan Mishchenko,
Robert K. Brayton:
Topologically constrained logic synthesis.
ICCAD 2002: 679-686 |
| 5 | EE | Robert K. Brayton,
M. Gao,
Jie-Hong Roland Jiang,
Yunjian Jiang,
Yinghua Li,
Alan Mishchenko,
Subarnarekha Sinha,
Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks.
ISMVL 2002: 168- |
| 4 | | Subarnarekha Sinha,
Alan Mishchenko,
Robert K. Brayton:
Topologically Constrained Logic Synthesis.
IWLS 2002: 13-20 |
| 2001 |
|---|
| 3 | EE | Subarnarekha Sinha,
Andreas Kuehlmann,
Robert K. Brayton:
Sequential SPFDs.
ICCAD 2001: 84-90 |
| 2000 |
|---|
| 2 | EE | Subarnarekha Sinha,
Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.
ICCD 2000: 494-503 |
| 1998 |
|---|
| 1 | EE | Subarnarekha Sinha,
Robert K. Brayton:
Implementation and use of SPFDs in optimizing Boolean networks.
ICCAD 1998: 103-110 |
