| 2007 |
|---|
| 8 | EE | Valavan Manohararajah,
Gordon R. Chiu,
Deshanand P. Singh,
Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.
IEEE Trans. VLSI Syst. 15(8): 895-903 (2007) |
| 2006 |
|---|
| 7 | EE | Valavan Manohararajah,
Stephen Dean Brown,
Zvonko G. Vranesic:
Adaptive FPGAs: High-Level Architecture and a Synthesis Method.
FPL 2006: 1-8 |
| 6 | EE | Gordon R. Chiu,
Deshanand P. Singh,
Valavan Manohararajah,
Stephen Dean Brown:
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.
ICCAD 2006: 135-142 |
| 5 | EE | Valavan Manohararajah,
Gordon R. Chiu,
Deshanand P. Singh,
Stephen Dean Brown:
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.
SLIP 2006: 3-8 |
| 4 | EE | Valavan Manohararajah,
Stephen Dean Brown,
Zvonko G. Vranesic:
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2331-2340 (2006) |
| 2005 |
|---|
| 3 | EE | Deshanand P. Singh,
Valavan Manohararajah,
Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis.
DAC 2005: 433-438 |
| 2 | | Valavan Manohararajah,
Deshanand P. Singh,
Stephen Dean Brown:
Post-Placement BDD-Based Decomposition for FPGAs.
FPL 2005: 31-38 |
| 2002 |
|---|
| 1 | EE | Valavan Manohararajah,
Terry Borer,
Stephen Dean Brown,
Zvonko G. Vranesic:
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.
FPL 2002: 232-241 |
