Ronald D. Blanton
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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61 | EE | Xiaochun Yu, R. D. (Shawn) Blanton: Multiple defect diagnosis using no assumptions on failing pattern characteristics. DAC 2008: 361-366 |
60 | EE | Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton: Precise failure localization using automated layout analysis of diagnosis candidates. DAC 2008: 367-372 |
59 | EE | Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi: Automated Testability Enhancements for Logic Brick Libraries. DATE 2008: 480-485 |
58 | EE | Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton: Physically-Aware N-Detect Test Pattern Selection. DATE 2008: 634-639 |
57 | EE | Jason G. Brown, R. D. (Shawn) Blanton: Automated Standard Cell Library Analysis for Improved Defect Modeling. ISQED 2008: 643-648 |
56 | EE | Sounil Biswas, R. D. (Shawn) Blanton: Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. VTS 2008: 299-308 |
2007 | ||
55 | EE | Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi: Specification Test Compaction for Analog Circuits and MEMS CoRR abs/0710.4719: (2007) |
54 | EE | Jason G. Brown, R. D. (Shawn) Blanton: A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. J. Electronic Testing 23(2-3): 131-144 (2007) |
2006 | ||
53 | EE | Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton: Multiple-detect ATPG based on physical neighborhoods. DAC 2006: 1099-1102 |
52 | EE | Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton: Extraction of defect density and size distributions from wafer sort test results. DATE 2006: 913-918 |
51 | EE | Jason G. Brown, R. D. (Shawn) Blanton: Exploiting Regularity for Inductive Fault Analysis. VTS 2006: 364-369 |
50 | EE | Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer: Extracting Defect Density and Size Distributions from Product ICs. IEEE Design & Test of Computers 23(5): 390-400 (2006) |
49 | EE | Sounil Biswas, Ronald D. Blanton: Statistical Test Compaction Using Binary Decision Trees. IEEE Design & Test of Computers 23(6): 452-462 (2006) |
48 | EE | Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni: Defect Modeling Using Fault Tuples. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2450-2464 (2006) |
47 | EE | Tao Jiang, R. D. (Shawn) Blanton: Inductive fault analysis of surface-micromachined MEMS. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1104-1116 (2006) |
2005 | ||
46 | EE | Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi: Specification Test Compaction for Analog Circuits and MEMS. DATE 2005: 164-169 |
45 | EE | R. D. (Shawn) Blanton, Subhasish Mitra: Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. VLSI Design 2005: 8-9 |
44 | EE | Rao Desineni, R. D. (Shawn) Blanton: Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. VTS 2005: 366-373 |
2004 | ||
43 | EE | Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton: Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. ISVLSI 2004: 173-178 |
42 | EE | Jason G. Brown, R. D. (Shawn) Blanton: CAEN-BIST: Testing the NanoFabric. ITC 2004: 462-471 |
41 | EE | Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, V. Rovner, S. Tiwary: Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC 2004: 508-517 |
40 | EE | Nilmoni Deb, R. D. (Shawn) Blanton: Multi-Modal Built-In Self-Test for Symmetric Microsystems. VTS 2004: 139-147 |
39 | EE | Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton: Generalized Sensitization using Fault Tuples. VTS 2004: 297-303 |
2003 | ||
38 | EE | Rahul Kundu, R. D. (Shawn) Blanton: ATPG for Noise-Induced Switch Failures in Domino Logic. ICCAD 2003: 765-769 |
37 | EE | Rahul Kundu, R. D. (Shawn) Blanton: Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. ITC 2003: 122-130 |
36 | EE | Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton: Progressive Bridge Identification. ITC 2003: 309-318 |
35 | EE | Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey: Deformations of IC Structure in Test and Yield Learning. ITC 2003: 856-865 |
34 | EE | R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah: Analyzing the Effectiveness of Multiple-Detect Test Sets. ITC 2003: 876-885 |
33 | EE | Ronald D. Blanton, John P. Hayes: On the properties of the input pattern fault model. ACM Trans. Design Autom. Electr. Syst. 8(1): 108-124 (2003) |
2002 | ||
32 | EE | Nilmoni Deb, R. D. (Shawn) Blanton: Built-In Self Test of CMOS-MEMS Accelerometers. ITC 2002: 1075-1084 |
31 | EE | Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels: Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC 2002: 233-241 |
30 | EE | Kumar N. Dwarakanath, R. D. (Shawn) Blanton: Exploiting Dominance and Equivalence using Fault Tuples. VTS 2002: 269-274 |
29 | EE | Rahul Kundu, R. D. (Shawn) Blanton: Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. VTS 2002: 379-388 |
28 | EE | Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim: SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS 2002: 449-450 |
27 | EE | Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly: Modeling the Economics of Testing: A DFT Perspective. IEEE Design & Test of Computers 19(1): 29-41 (2002) |
26 | EE | Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton: Test vector generation for charge sharing failures in dynamic logic. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1502-1508 (2002) |
2001 | ||
25 | EE | Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi: False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731 |
24 | EE | Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton: Testing of Dynamic Logic Circuits Based on Charge Sharing. VTS 2001: 396-403 |
2000 | ||
23 | EE | Kumar N. Dwarakanath, Ronald D. Blanton: Universal fault simulation using fault tuples. DAC 2000: 786-789 |
22 | Rahul Kundu, Ronald D. Blanton: Identification of crosstalk switch failures in domino CMOS circuits. ITC 2000: 502-509 | |
21 | Nilmoni Deb, Ronald D. Blanton: Analysis of failure sources in surface-micromachined MEMS. ITC 2000: 739-749 | |
20 | Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton: Universal test generation using fault tuples. ITC 2000: 812-819 | |
19 | EE | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen: Effectiveness of Microarchitecture Test Program Generation. IEEE Design & Test of Computers 17(4): 38-49 (2000) |
18 | EE | Ronald D. Blanton, John P. Hayes: On the design of fast, easily testable ALU's. IEEE Trans. VLSI Syst. 8(2): 220-223 (2000) |
17 | EE | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen: A Buffer-Oriented Methodology for Microarchitecture Validation. J. Electronic Testing 16(1-2): 49-65 (2000) |
1999 | ||
16 | Tao Jiang, Ronald D. Blanton: Particulate failures for surface-micromachined MEMS. ITC 1999: 329-337 | |
15 | EE | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen: Superscalar Processor Validation at the Microarchitecture Level. VLSI Design 1999: 300-305 |
14 | EE | R. D. (Shawn) Blanton: IDDQ-Testability of Tree Circuits. VLSI Design 1999: 78-86 |
13 | Bernard Courtois, R. D. (Shawn) Blanton: Guest Editors' Introduction. IEEE Design & Test of Computers 16(4): 16-17 (1999) | |
12 | EE | Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton: Hierarchical Design and Test of Integrated Microsystems. IEEE Design & Test of Computers 16(4): 18-27 (1999) |
1998 | ||
11 | EE | Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla: Failure modes for stiction in surface-micromachined MEMS. ITC 1998: 551-556 |
10 | EE | Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton: MEMS fault model generation using CARAMEL. ITC 1998: 557- |
1997 | ||
9 | EE | Ronald D. Blanton, John P. Hayes: The input pattern fault model and its application. ED&TC 1997: 628 |
8 | Ronald D. Blanton, John P. Hayes: Properties of the Input Pattern Fault Model. ICCD 1997: 372-380 | |
7 | Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly: To DFT or Not to DFT? ITC 1997: 557-566 | |
6 | Abhijeet Kolpekwar, Ronald D. Blanton: Development of a MEMS Testing Methodology. ITC 1997: 923-931 | |
5 | EE | R. D. (Shawn) Blanton, John P. Hayes: Testability Properties of Divergent Trees. J. Electronic Testing 11(3): 197-209 (1997) |
1996 | ||
4 | Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani: Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC 1996: 757-766 | |
3 | EE | R. D. (Shawn) Blanton, John P. Hayes: Design of a fast, easily testable ALU. VTS 1996: 9-16 |
2 | Ronald D. Blanton, John P. Hayes: Testability of Convergent Tree Circuits. IEEE Trans. Computers 45(8): 950-963 (1996) | |
1993 | ||
1 | Ronald D. Blanton, John P. Hayes: Efficient Testing of Tree Circuits. FTCS 1993: 176-185 |