| 2009 |
|---|
| 177 | EE | Kunal P. Ganeshpure,
Ilia Polian,
Sandip Kundu,
Bernd Becker:
Reducing temperature variability by routing heat pipes.
ACM Great Lakes Symposium on VLSI 2009: 63-68 |
| 176 | EE | Alejandro Czutro,
Ilia Polian,
Matthew Lewis,
Piet Engelke,
Sudhakar M. Reddy,
Bernd Becker:
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
VLSI Design 2009: 227-232 |
| 175 | EE | Ralf Wimmer,
Bettina Braitling,
Bernd Becker:
Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking.
VMCAI 2009: 366-380 |
| 174 | EE | Eckard Böde,
Marc Herbstritt,
Holger Hermanns,
Sven Johr,
Thomas Peikenkamp,
Reza Pulungan,
Jan Rakow,
Ralf Wimmer,
Bernd Becker:
Compositional Dependability Evaluation for STATEMATE.
IEEE Trans. Software Eng. 35(2): 274-292 (2009) |
| 2008 |
|---|
| 173 | EE | Piet Engelke,
Ilia Polian,
Jürgen Schlöffel,
Bernd Becker:
Resistive Bridging Fault Simulation of Industrial Circuits.
DATE 2008: 628-633 |
| 172 | EE | Ralf Wimmer,
Alexander Kortus,
Marc Herbstritt,
Bernd Becker:
Probabilistic Model Checking and Reliability of Results.
DDECS 2008: 207-212 |
| 171 | EE | Ilia Polian,
Kohei Miyase,
Yusuke Nakamura,
Seiji Kajihara,
Piet Engelke,
Bernd Becker,
Stefan Spinner,
Xiaoqing Wen:
Diagnosis of Realistic Defects Based on the X-Fault Model.
DDECS 2008: 263-266 |
| 170 | EE | Ilia Polian,
Sudhakar M. Reddy,
Irith Pomeranz,
Xun Tang,
Bernd Becker:
On Reducing Circuit Malfunctions Caused by Soft Errors.
DFT 2008: 245-253 |
| 169 | EE | Damian Nowroth,
Ilia Polian,
Bernd Becker:
A study of cognitive resilience in a JPEG compressor.
DSN 2008: 32-41 |
| 168 | EE | Bernd Becker,
Marc Herbstritt,
Natalia Kalinnik,
Matthew D. T. Lewis,
Juri Lichtner,
Tobias Nopper,
Ralf Wimmer:
Propositional approximations for bounded model checking of partial circuit designs.
ICCD 2008: 52-59 |
| 167 | EE | Ilia Polian,
Sudhakar M. Reddy,
Bernd Becker:
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
ISVLSI 2008: 257-262 |
| 166 | EE | Stefan Spinner,
Ilia Polian,
Piet Engelke,
Bernd Becker,
Martin Keim,
Wu-Tung Cheng:
Automatic Test Pattern Generation for Interconnect Open Defects.
VTS 2008: 181-186 |
| 165 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Sandip Kundu,
Bharath Seshadri,
Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008) |
| 2007 |
|---|
| 164 | EE | Ralf Wimmer,
Marc Herbstritt,
Bernd Becker:
Optimization techniques for BDD-based bisimulation computation.
ACM Great Lakes Symposium on VLSI 2007: 405-410 |
| 163 | EE | Matthew D. T. Lewis,
Tobias Schubert,
Bernd Becker:
Multithreaded SAT Solving.
ASP-DAC 2007: 926-931 |
| 162 | EE | Bernd Becker,
Christian Dax,
Jochen Eisinger,
Felix Klaedtke:
LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals.
CAV 2007: 307-310 |
| 161 | | Marc Herbstritt,
Bernd Becker,
Erika Ábrahám,
Christian Herde:
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.
DDECS 2007: 391-396 |
| 160 | EE | Marc Herbstritt,
Bernd Becker:
On Combining 01X-Logic and QBF.
EUROCAST 2007: 531-538 |
| 159 | EE | Tobias Nopper,
Christoph Scholl,
Bernd Becker:
Computation of minimal counterexamples by using black box techniques and symbolic methods.
ICCAD 2007: 273-280 |
| 158 | EE | Ilia Polian,
Damian Nowroth,
Bernd Becker:
Identification of Critical Errors in Imaging Applications.
IOLTS 2007: 201-202 |
| 157 | EE | Marc Herbstritt,
Vanessa Struve,
Bernd Becker:
Application of Lifting in Partial Design Analysis.
MTV 2007: 33-38 |
| 156 | EE | John P. Hayes,
Ilia Polian,
Bernd Becker:
An Analysis Framework for Transient-Error Tolerance.
VTS 2007: 249-255 |
| 155 | EE | Ilia Polian,
Alejandro Czutro,
Bernd Becker:
Evolutionary Optimization in Code-Based Test Compression
CoRR abs/0710.4670: (2007) |
| 154 | EE | Stefan Spinner,
J. Bartholomeyczik,
Bernd Becker,
M. Doelle,
O. Paul,
Ilia Polian,
R. Roth,
K. Seitz,
P. Ruther:
Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors
CoRR abs/0711.3289: (2007) |
| 153 | EE | Erika Ábrahám,
Marc Herbstritt,
Bernd Becker,
Martin Steffen:
Bounded Model Checking with Parametric Data Structures.
Electr. Notes Theor. Comput. Sci. 174(3): 3-16 (2007) |
| 152 | EE | Ilia Polian,
Alejandro Czutro,
Sandip Kundu,
Bernd Becker:
Power Droop Testing.
IEEE Design & Test of Computers 24(3): 276-284 (2007) |
| 151 | EE | Bernd Becker,
Andreas Podelski,
Werner Damm,
Martin Fränzle,
Ernst-Rüdiger Olderog,
Reinhard Wilhelm:
SFB/TR 14 AVACS - Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS - Automatische Verifikation und Analyse komplexer Systeme).
it - Information Technology 49(2): 118- (2007) |
| 2006 |
|---|
| 150 | EE | Ralf Wimmer,
Marc Herbstritt,
Holger Hermanns,
Kelley Strampp,
Bernd Becker:
Sigref- A Symbolic Bisimulation Tool Box.
ATVA 2006: 477-492 |
| 149 | | Jochen Eisinger,
Ilia Polian,
Bernd Becker,
Alexander Metzner,
Stephan Thesing,
Reinhard Wilhelm:
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.
DDECS 2006: 15-20 |
| 148 | | Ralf Wimmer,
Marc Herbstritt,
Bernd Becker:
Minimization of Large State Spaces using Symbolic Branching Bisimulation.
DDECS 2006: 9-14 |
| 147 | EE | Ilia Polian,
Bernd Becker,
Masato Nakasato,
Satoshi Ohtake,
Hideo Fujiwara:
Low-Cost Hardening of Image Processing Applications Against Soft Errors.
DFT 2006: 274-279 |
| 146 | EE | Erika Ábrahám,
Tobias Schubert,
Bernd Becker,
Martin Fränzle,
Christian Herde:
Parallel SAT Solving in Bounded Model Checking.
FMICS/PDMC 2006: 301-315 |
| 145 | EE | Ilia Polian,
Alejandro Czutro,
Sandip Kundu,
Bernd Becker:
Power Droop Testing.
ICCD 2006 |
| 144 | EE | Marc Herbstritt,
Bernd Becker,
Christoph Scholl:
Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs.
MTV 2006: 37-44 |
| 143 | EE | Eckard Böde,
Marc Herbstritt,
Holger Hermanns,
Sven Johr,
Thomas Peikenkamp,
Reza Pulungan,
Ralf Wimmer,
Bernd Becker:
Compositional Performability Evaluation for STATEMATE.
QEST 2006: 167-178 |
| 142 | EE | Jan Reineke,
Björn Wachter,
Stephan Thesing,
Reinhard Wilhelm,
Ilia Polian,
Jochen Eisinger,
Bernd Becker:
A Definition and Classification of Timing Anomalies.
WCET 2006 |
| 141 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Piet Engelke,
Ilia Polian,
Bernd Becker,
Jürgen Schlöffel,
Friedrich Hapke,
Michael Wittke:
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. VLSI Syst. 14(2): 193-202 (2006) |
| 140 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bernd Becker:
Simulating Resistive-Bridging and Stuck-At Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006) |
| 139 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bernd Becker:
Automatic Test Pattern Generation for Resistive Bridging Faults.
J. Electronic Testing 22(1): 61-69 (2006) |
| 138 | EE | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Orthogonal Hypergraph Drawing for Improved Visibility.
J. Graph Algorithms Appl. 10(2): 141-157 (2006) |
| 137 | EE | Bernd Becker,
Ilia Polian,
Sybille Hellebrand,
Bernd Straube,
Hans-Joachim Wunderlich:
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it - Information Technology 48(5): 304- (2006) |
| 2005 |
|---|
| 136 | EE | Sandip Kundu,
Piet Engelke,
Ilia Polian,
Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Asian Test Symposium 2005: 266-271 |
| 135 | EE | Ilia Polian,
Thomas Fiehn,
Bernd Becker,
John P. Hayes:
A Family of Logical Fault Models for Reversible Circuits.
Asian Test Symposium 2005: 422-427 |
| 134 | EE | Ilia Polian,
Alejandro Czutro,
Bernd Becker:
Evolutionary Optimization in Code-Based Test Compression.
DATE 2005: 1124-1129 |
| 133 | EE | Tobias Schubert,
Bernd Becker:
Lemma Exchange in a Microcontroller Based Parallel SAT Solver.
ISVLSI 2005: 142-147 |
| 132 | EE | Marc Herbstritt,
Bernd Becker:
On SAT-based Bounded Invariant Checking of Blackbox Designs.
MTV 2005: 23-28 |
| 131 | EE | Tobias Schubert,
Matthew D. T. Lewis,
Bernd Becker:
PaMira - A Parallel SAT Solver with Knowledge Sharing.
MTV 2005: 29-36 |
| 130 | | Tobias Schubert,
Bernd Becker:
Knowledge Sharing in a Microcontroller based Parallel SAT Solver.
PDPTA 2005: 1049-1055 |
| 129 | EE | Jochen Eisinger,
Peter Winterer,
Bernd Becker:
Securing Wireless Networks in a University Environment.
PerCom Workshops 2005: 312-316 |
| 128 | EE | Matthew D. T. Lewis,
Tobias Schubert,
Bernd Becker:
Speedup Techniques Utilized in Modern SAT Solvers.
SAT 2005: 437-443 |
| 127 | EE | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.
VLSI Design 2005: 433-438 |
| 126 | EE | Erika Ábrahám,
Bernd Becker,
Felix Klaedtke,
Martin Steffen:
Optimizing Bounded Model Checking for Linear Hybrid Systems.
VMCAI 2005: 396-412 |
| 125 | EE | Ilia Polian,
Sandip Kundu,
Jean Marc Gallière,
Piet Engelke,
Michel Renovell,
Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
VTS 2005: 343-348 |
| 124 | EE | Bernd Becker,
Markus Behle,
Friedrich Eisenbrand,
Ralf Wimmer:
BDDs in a Branch and Cut Framework.
WEA 2005: 452-463 |
| 123 | EE | Ilia Polian,
Piet Engelke,
Michel Renovell,
Bernd Becker:
Modeling Feedback Bridging Faults with Non-Zero Resistance.
J. Electronic Testing 21(1): 57-69 (2005) |
| 2004 |
|---|
| 122 | EE | Tobias Schubert,
Bernd Becker:
Parallel SAT Solving with Microcontrollers.
AACC 2004: 59-67 |
| 121 | EE | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Orthogonal hypergraph routing for improved visibility.
ACM Great Lakes Symposium on VLSI 2004: 385-388 |
| 120 | | Tobias Schubert,
Bernd Becker:
A Distributed SAT Solver for Microcontroller.
ARCS Workshops 2004: 338-347 |
| 119 | EE | John P. Hayes,
Ilia Polian,
Bernd Becker:
Testing for Missing-Gate Faults in Reversible Circuits.
Asian Test Symposium 2004: 100-105 |
| 118 | | Thomas Eschbach,
Rolf Dreschler,
Bernd Becker:
Placement and routing optimization for circuits derived from BDDs.
ISCAS (5) 2004: 229-232 |
| 117 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Piet Engelke,
Ilia Polian,
Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage.
ITC 2004: 442-451 |
| 116 | EE | Marc Herbstritt,
Thomas Kmieciak,
Bernd Becker:
On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification.
MTV 2004: 50-55 |
| 115 | EE | Tobias Schubert,
Bernd Becker:
PICHAFF2 - A Hierarchical Parallel SAT Solver.
MTV 2004: 56-61 |
| 114 | EE | Matthew D. T. Lewis,
Tobias Schubert,
Bernd Becker:
Early Conflict Detection Based BCP for SAT Solving.
SAT 2004 |
| 113 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bharath Seshadri,
Bernd Becker:
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
VTS 2004: 171-178 |
| 112 | EE | Ilia Polian,
Bernd Becker:
Scalable Delay Fault BIST for Use with Low-Cost ATE.
J. Electronic Testing 20(2): 181-197 (2004) |
| 2003 |
|---|
| 111 | EE | Ilia Polian,
Bernd Becker,
Sudhakar M. Reddy:
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.
DATE 2003: 11184-11185 |
| 110 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bernd Becker:
Simulating Resistive Bridging and Stuck-At Faults.
ITC 2003: 1051-1059 |
| 109 | EE | Marc Herbstritt,
Bernd Becker:
Conflict-Based Selection of Branching Rules.
SAT 2003: 441-451 |
| 108 | | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Cross Reduction for Orthogonal Circuit Visualization.
VLSI 2003: 107-113 |
| 107 | | Ilia Polian,
Bernd Becker:
Reducing ATE Cost in System-on-Chip Test.
VLSI-SOC 2003: 337-342 |
| 106 | | Martin Keim,
Rolf Drechsler,
Bernd Becker,
Michael Martin,
Paul Molitor:
Polynomial Formal Verification of Multipliers.
Formal Methods in System Design 22(1): 39-58 (2003) |
| 105 | EE | Frank Schmiedle,
Rolf Drechsler,
Bernd Becker:
Exact Routing with Search Space Reduction.
IEEE Trans. Computers 52(6): 815-825 (2003) |
| 104 | EE | Ilia Polian,
Wolfgang Günther,
Bernd Becker:
Pattern-based verification of connections to intellectual property cores.
Integration 35(1): 25-44 (2003) |
| 103 | EE | Ilia Polian,
Bernd Becker:
Multiple Scan Chain Design for Two-Pattern Testing.
J. Electronic Testing 19(1): 37-48 (2003) |
| 102 | EE | Jonathan Bradford,
Hartmut Delong,
Ilia Polian,
Bernd Becker:
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.
J. Electronic Testing 19(4): 387-395 (2003) |
| 2002 |
|---|
| 101 | EE | Ilia Polian,
Irith Pomeranz,
Bernd Becker:
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Asian Test Symposium 2002: 2-14 |
| 100 | EE | Thomas Eschbach,
Wolfgang Günther,
Rolf Drechsler,
Bernd Becker:
Crossing Reduction by Windows Optimization.
Graph Drawing 2002: 285-294 |
| 99 | EE | Christoph Scholl,
Bernd Becker:
Checking Equivalence for Circuits Containing Incompletely Specified Boxes.
ICCD 2002: 56-63 |
| 98 | EE | Ilia Polian,
Bernd Becker:
Stop & Go BIST.
IOLTW 2002: 147-151 |
| 97 | EE | Ilia Polian,
Martin Keim,
Nicolai Mallig,
Bernd Becker:
Sequential n -Detection Criteria: Keep It Simple.
IOLTW 2002: 189 |
| 96 | EE | Ilia Polian,
Piet Engelke,
Bernd Becker:
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.
ISMVL 2002: 216- |
| 95 | | Christoph Scholl,
Bernd Becker,
Thomas M. Weis:
On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division.
Formal Methods in System Design 20(3): 311-326 (2002) |
| 2001 |
|---|
| 94 | EE | Christoph Scholl,
Bernd Becker,
Andreas Brogle:
The multiple variable order problem for binary decision diagrams: theory and practical application.
ASP-DAC 2001: 85-90 |
| 93 | EE | Wolfgang Günther,
Andreas Hett,
Bernd Becker:
Application of linearly transformed BDDs in sequential verification.
ASP-DAC 2001: 91-96 |
| 92 | EE | Ilia Polian,
Wolfgang Günther,
Bernd Becker:
Efficient Pattern-Based Verification of Connections to IP Cores .
Asian Test Symposium 2001: 443-448 |
| 91 | EE | Christoph Scholl,
Bernd Becker:
Checking Equivalence for Partial Implementations.
DAC 2001: 238-243 |
| 90 | EE | Bernd Becker,
Thomas Eschbach,
Rolf Drechsler,
Wolfgang Günther:
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
DSD 2001: 54-61 |
| 89 | EE | Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Multi-objective Optimisation Based on Relation Favour.
EMO 2001: 154-166 |
| 88 | EE | Frank Schmiedle,
Daniel Große,
Rolf Drechsler,
Bernd Becker:
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics.
Fuzzy Days 2001: 479-491 |
| 87 | EE | Christoph Scholl,
Marc Herbstritt,
Bernd Becker:
Exploiting don't cares to minimize *BMDs.
ISCAS (5) 2001: 191-194 |
| 86 | EE | Ilia Polian,
Bernd Becker:
Multiple Scan Chain Design for Two-Pattern Testing.
VTS 2001: 88-93 |
| 85 | EE | Martin Keim,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.
J. Electronic Testing 17(1): 37-51 (2001) |
| 2000 |
|---|
| 84 | EE | Andreas Hett,
Christoph Scholl,
Bernd Becker:
Distance driven finite state machine traversal.
DAC 2000: 39-42 |
| 83 | EE | Christoph Scholl,
Bernd Becker:
On the Generation of Multiplexer Circuits for Pass Transistor Logic.
DATE 2000: 372- |
| 82 | EE | Wolfgang Günther,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Verification of Designs Containing Black Boxes.
EUROMICRO 2000: 1100-1105 |
| 81 | EE | Rolf Drechsler,
Wolfgang Günther,
Bernd Becker:
Testability of Circuits Derived from Lattice Diagrams.
EUROMICRO 2000: 1188-1192 |
| 80 | EE | Rolf Drechsler,
Nicole Drechsler,
Elke Mackensen,
Tobias Schubert,
Bernd Becker:
Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System.
EUROMICRO 2000: 1425- |
| 79 | | Tobias Schubert,
Elke Mackensen,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Specialized Hardware for Implementation of Evolutionary Algorithms.
GECCO 2000: 369 |
| 78 | EE | Wolfgang Günther,
Robby Schönfeld,
Bernd Becker,
Paul Molitor:
k-Layer Straightline Crossing Minimization by Speeding Up Sifting.
Graph Drawing 2000: 253-258 |
| 77 | EE | Per Lindgren,
Rolf Drechsler,
Bernd Becker:
Minimization of Ordered Pseudo Kronecker Decision Diagrams.
ICCD 2000: 504- |
| 76 | EE | Frank Schmiedle,
Daniel Unruh,
Bernd Becker:
Exact switchbox routing with search space reduction.
ISPD 2000: 26-32 |
| 75 | EE | Rolf Drechsler,
Bernd Becker,
Nicole Drechsler:
OKFDD minimization by genetic algorithms with application to circuit design.
Integration 28(2): 121-139 (2000) |
| 1999 |
|---|
| 74 | EE | Martin Keim,
Nicole Drechsler,
Bernd Becker:
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.
ASP-DAC 1999: 315-318 |
| 73 | EE | Harry Hengster,
Bernd Becker:
Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.
FTCS 1999: 268-275 |
| 72 | | Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes.
Fuzzy Days 1999: 108-117 |
| 71 | EE | Per Lindgren,
Rolf Drechsler,
Bernd Becker:
Synthesis of Pseudo Kronecker Lattice Diagrams.
ICCD 1999: 307-310 |
| 70 | EE | Rolf Drechsler,
Marc Herbstritt,
Bernd Becker:
Grouping heuristics for word-level decision diagrams.
ISCAS (1) 1999: 411-414 |
| 69 | EE | Frank Schmiedle,
Rolf Drechsler,
Bernd Becker:
Exact channel routing using symbolic representation.
ISCAS (6) 1999: 394-397 |
| 68 | EE | Rolf Drechsler,
Harry Hengster,
Horst Schäfer,
Joachim Hartmann,
Bernd Becker:
Testability of 2-Level AND/EXOR Circuits.
J. Electronic Testing 14(3): 219-225 (1999) |
| 67 | EE | Bernd Becker,
Martin Keim,
Rolf Krieger:
Hybrid Fault Simulation for Synchronous Sequential Circuits.
J. Electronic Testing 15(3): 219-238 (1999) |
| 1998 |
|---|
| 66 | EE | Christoph Scholl,
Bernd Becker,
Thomas M. Weis:
Word-level decision diagrams, WLCDs and division.
ICCAD 1998: 672-677 |
| 65 | EE | Martin Keim,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.
ISMVL 1998: 215- |
| 64 | EE | Per Lindgren,
Rolf Drechsler,
Bernd Becker:
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.
ISMVL 1998: 95- |
| 63 | | Rolf Drechsler,
Bernd Becker,
Andrea Jahnke:
On Variable Ordering and Decomposition Type Choice in OKFDDs.
IEEE Trans. Computers 47(12): 1398-1403 (1998) |
| 62 | EE | Rolf Drechsler,
Bernd Becker:
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 965-973 (1998) |
| 61 | EE | Bernd Becker:
Testing with decision diagrams.
Integration 26(1-2): 5-20 (1998) |
| 1997 |
|---|
| 60 | EE | Andreas Hett,
Rolf Drechsler,
Bernd Becker:
Fast and efficient construction of BDDs by reordering based synthesis.
ED&TC 1997: 168-175 |
| 59 | EE | Rolf Drechsler,
Harry Hengster,
Horst Schäfer,
Joachim Hartmann,
Bernd Becker:
Testability of 2-level AND/EXOR circuits.
ED&TC 1997: 548-553 |
| 58 | EE | Christoph Scholl,
Rolf Drechsler,
Bernd Becker:
Functional simulation using binary decision diagrams.
ICCAD 1997: 8-12 |
| 57 | EE | Rolf Drechsler,
Martin Keim,
Bernd Becker:
Fault Simulation in Sequential Multi-Valued Logic Networks.
ISMVL 1997: 145- |
| 56 | EE | Rolf Drechsler,
Martin Keim,
Bernd Becker:
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.
ISMVL 1997: 66- |
| 55 | | Rolf Drechsler,
Bernd Becker,
Stefan Ruppertz:
Manipulation Algorithms for K*BMDs.
TACAS 1997: 4-18 |
| 54 | EE | Bernd Becker,
Rolf Drechsler,
Sudhakar M. Reddy:
(Quasi-) Linear Path Delay Fault Tests for Adders.
VLSI Design 1997: 101-105 |
| 53 | EE | Bernd Becker,
Rolf Drechsler:
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions.
VLSI Design 1997: 46-50 |
| 52 | EE | Martin Keim,
Michael Martin,
Bernd Becker,
Rolf Drechsler,
Paul Molitor:
Polynomial Formal Verification of Multipliers.
VTS 1997: 150-157 |
| 51 | EE | Can Ökmen,
Martin Keim,
Rolf Krieger,
Bernd Becker:
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.
VTS 1997: 426-433 |
| 50 | | Bernd Becker,
Rolf Drechsler,
Michael Theobald:
On the Expressive Power of OKFDDs.
Formal Methods in System Design 11(1): 5-21 (1997) |
| 49 | EE | Rolf Drechsler,
Bernd Becker,
Stefan Ruppertz:
The K*BMD: A Verification Data Structure.
IEEE Design & Test of Computers 14(2): 51-59 (1997) |
| 48 | EE | Rolf Drechsler,
Bernd Becker:
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 1-5 (1997) |
| 1996 |
|---|
| 47 | EE | Harry Hengster,
Rolf Drechsler,
Bernd Becker,
Stefan Eckrich,
Tonja Pfeiffer:
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.
Asian Test Symposium 1996: 148- |
| 46 | | Harry Hengster,
Uwe Sparmann,
Bernd Becker,
Sudhakar M. Reddy:
Local Transformations and Robust Dependent Path Delay.
ITC 1996: 347-356 |
| 45 | | Rolf Drechsler,
Nicole Göckel,
Bernd Becker:
Learning Heuristics for OBDD Minimization by Evolutionary Algorithms.
PPSN 1996: 730-739 |
| 44 | EE | Martin Keim,
Bernd Becker,
Birgitta Stenner:
On the (non-)resetability of synchronous sequential circuits.
VTS 1996: 240-245 |
| 43 | | Rolf Drechsler,
Michael Theobald,
Bernd Becker:
Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.
IEEE Trans. Computers 45(11): 1294-1299 (1996) |
| 1995 |
|---|
| 42 | EE | Rolf Drechsler,
Bernd Becker:
Learning heuristics by genetic algorithms.
ASP-DAC 1995 |
| 41 | EE | Rolf Krieger,
Bernd Becker,
Martin Keim:
Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy.
DAC 1995: 339-344 |
| 40 | | Rolf Krieger,
Bernd Becker,
Can Ökmen:
OBDD-based Optimization of Input Probabilities for Weighted Random Pattern Generation.
FTCS 1995: 120-129 |
| 39 | | Bernd Becker,
Rolf Drechsler,
Michael Theobald:
OKFDDs versus OBDDs and OFDDs.
ICALP 1995: 475-486 |
| 38 | EE | Rolf Drechsler,
Bernd Becker:
Dynamic minimization of OKFDDs.
ICCD 1995: 602- |
| 37 | EE | Rolf Drechsler,
Rolf Krieger,
Bernd Becker:
Random Pattern Fault Simulation in Multi-Valued Circuits.
ISMVL 1995: 98-103 |
| 36 | | Bernd Becker,
Rolf Drechsler,
Ralph Werchner:
On the Relation Betwen BDDs and FDDs.
LATIN 1995: 72-83 |
| 35 | EE | Harry Hengster,
Rolf Drechsler,
Bernd Becker:
On the application of local circuit transformations with special emphasis on path delay fault testability.
VTS 1995: 387-392 |
| 34 | EE | Bernd Becker,
Rolf Drechsler,
Paul Molitor:
On the generation of area-time optimal testable adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1049-1066 (1995) |
| 33 | | Bernd Becker,
Rolf Drechsler,
Ralph Werchner:
On the Relation between BDDs and FDDs.
Inf. Comput. 123(2): 185-197 (1995) |
| 32 | EE | Harry Hengster,
Rolf Drechsler,
Bernd Becker:
On local transformations and path delay fault testability.
J. Electronic Testing 7(3): 173-191 (1995) |
| 1994 |
|---|
| 31 | EE | Rolf Drechsler,
Andisheh Sarabi,
Michael Theobald,
Bernd Becker,
Marek A. Perkowski:
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
DAC 1994: 415-419 |
| 30 | | Ralf Hahn,
Rolf Krieger,
Bernd Becker:
A Hierarchical Approach to Fault Collapsing.
EDAC-ETC-EUROASIC 1994: 171-176 |
| 29 | | Bernd Becker,
Rolf Drechsler:
Testability of Circuits Derived from Functional Decision Diagrams.
EDAC-ETC-EUROASIC 1994: 667 |
| 28 | EE | Rolf Drechsler,
Bernd Becker,
Michael Theobald:
Fast OFDD based minimization of fixed polarity Reed-Muller expressions.
EURO-DAC 1994: 2-7 |
| 27 | | Bernd Becker,
Rolf Drechsler:
OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.
ICCD 1994: 106-110 |
| 26 | | Bernd Becker,
Rolf Drechsler:
Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms.
ISMVL 1994: 65-72 |
| 25 | | Rolf Krieger,
Bernd Becker,
Martin Keim:
A Hybrid Fault Simulator for Synchronous Sequential Circuits.
ITC 1994: 614-623 |
| 24 | | Harry Hengster,
Rolf Drechsler,
Bernd Becker:
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.
VLSI Design 1994: 123-126 |
| 1993 |
|---|
| 23 | | Rolf Krieger,
Bernd Becker,
R. Sinkovic:
A BDD - based Algorithm for Computation of Exact Fault Detection Probabilities.
FTCS 1993: 186-195 |
| 22 | | Bernd Becker,
Rolf Krieger:
FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits.
VLSI Design 1993: 128-131 |
| 1992 |
|---|
| 21 | | Bernd Becker,
Joachim Hartmann:
Some Remarks on the Test Complexity of Iterative Logic Arrays.
MFCS 1992: 142-152 |
| 20 | | Bernd Becker:
Synthesis for Testability: Binary Decision Diagrams.
STACS 1992: 501-512 |
| 1991 |
|---|
| 19 | | Bernd Becker,
Uwe Sparmann:
A uniform test approach for RCC-adders.
Fundam. Inform. 14(2): 185-219 (1991) |
| 18 | | Bernd Becker,
Uwe Sparmann:
Computations over Finite Monoids and their Test Complexity.
Theor. Comput. Sci. 84(2): 225-250 (1991) |
| 1990 |
|---|
| 17 | EE | Bernd Becker,
Thomas Burch,
Günter Hotz,
D. Kiel,
Reiner Kolla,
Paul Molitor,
Hans-Georg Osthof,
Gisela Pitsch,
Uwe Sparmann:
A graphical system for hierarchical specifications and checkups of VLSI circuits.
EURO-DAC 1990: 174-179 |
| 16 | EE | Bernd Becker,
Joachim Hartmann:
Optimal-Time Multipliers and C-Testability.
SPAA 1990: 146-154 |
| 15 | | Bernd Becker,
Joachim Hartmann:
Optimal-Time Multipliers and C-Testability.
Elektronische Informationsverarbeitung und Kybernetik 26(10): 547-561 (1990) |
| 1988 |
|---|
| 14 | | Bernd Becker,
Uwe Sparmann:
Regular Structures and Testing: RCC-Adders.
AWOC 1988: 288-300 |
| 13 | | Bernd Becker,
Reiner Kolla:
On the Construction of Optimal Time Adders (Extended Abstract).
STACS 1988: 18-28 |
| 12 | | Bernd Becker:
Efficient Testing of Optimal Time Adders.
IEEE Trans. Computers 37(9): 1113-1121 (1988) |
| 11 | | Bernd Becker,
Hans-Ulrich Simon:
How Robust Is The n-Cube?
Inf. Comput. 77(2): 162-178 (1988) |
| 1987 |
|---|
| 10 | EE | Bernd Becker,
Günter Hotz,
Reiner Kolla,
Paul Molitor,
Hans-Georg Osthof:
Hierarchical Design Based on a Calculus of Nets.
DAC 1987: 649-653 |
| 9 | | Bernd Becker:
An Easily Testable Optimal-Time VLSI-Multiplier.
Acta Inf. 24(4): 363-380 (1987) |
| 8 | | Bernd Becker,
Hans-Georg Osthof:
Layouts with Wires of Balanced Length
Inf. Comput. 73(1): 45-59 (1987) |
| 7 | | Bernd Becker,
Günter Hotz:
On the Optimal Layout of Planar Graphs with Fixed Boundary.
SIAM J. Comput. 16(5): 946-972 (1987) |
| 1986 |
|---|
| 6 | | Bernd Becker,
Hans-Ulrich Simon:
How Robust Is the n-Cube? (Extended Abstract)
FOCS 1986: 283-291 |
| 5 | | Bernd Becker:
Efficient Testing of Optimal Time Adders (Extended Abstract).
MFCS 1986: 218-229 |
| 4 | | Günter Hotz,
Bernd Becker,
Reiner Kolla,
Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform., Forsch. Entwickl. 1(1): 38-47 (1986) |
| 3 | | Günter Hotz,
Bernd Becker,
Reiner Kolla,
Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform., Forsch. Entwickl. 1(2): 72-82 (1986) |
| 1985 |
|---|
| 2 | | Bernd Becker,
Hans-Georg Osthof:
Layouts with Wires of Balanced Length.
STACS 1985: 21-31 |
| 1983 |
|---|
| 1 | | Bernd Becker:
On the crossing-free, rectangular embedding of weighted graphs in the plane.
Theoretical Computer Science 1983: 61-72 |
