Hao Zheng

2009
19	EE	Haiqiong Yao, Hao Zheng: Automated Interface Refinement for Compositional Verification. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 433-446 (2009)
2008
18	EE	Hao Zheng, Xian Wu, Yong Yu: Enriching WordNet with Folksonomies. PAKDD 2008: 1075-1080
17	EE	Hao Zheng, Jared Ahrens, Tian Xia: A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1343-1347 (2008)
2006
16	EE	Miao Xiong, Yifan Chen, Hao Zheng, Yong Yu: Towards Quick Understanding and Analysis of Large-Scale Ontologies. ASWC 2006: 84-98
15	EE	Di Mu, Tian Xia, Hao Zheng: Data Dependent Jitter Characterization Based on Fourier Analysis. DFT 2006: 534-544
14	EE	Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 403-412 (2006)
2005
13	EE	Tian Xia, Peilin Song, Hao Zheng: Characterizing the VCO jitter due to the digital simultaneous switching noise. ACM Great Lakes Symposium on VLSI 2005: 70-73
12	EE	Tian Xia, Hao Zheng, Jing Li, Ahmed Ginawi: Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators. ISVLSI 2005: 218-223
2004
11	EE	Tiehua Du, Kah Bin Lim, Geok Soon Hong, Wei Miao Yu, Hao Zheng: 2-D Occluded Object Recognition Using Wavelets. CIT 2004: 227-232
10	EE	Billy Lim, Hao Zheng: A day in the life of Jini: a peek at service-oriented architecture for internet appliances. IJMC 2(2): 199-216 (2004)
2003
9	EE	Michael Epstein, Laszlo Hars, Raymond Krasinski, Martin Rosner, Hao Zheng: Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts. CHES 2003: 152-165
8	EE	Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35
7	EE	Hao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003)
2001
6	EE	Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340
5	EE	Hao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193
1999
4	EE	Brandon M. Bachman, Hao Zheng, Chris J. Myers: Architectural Synthesis of Timed Asynchronous Systems. ICCD 1999: 354-363
3		Jianer Chen, Donald K. Friesen, Hao Zheng: Tight Bound on Johnson's Algorithm for Maximum Satisfiability. J. Comput. Syst. Sci. 58(3): 622-640 (1999)
1997
2	EE	Jianer Chen, Donald K. Friesen, Hao Zheng: Tight Bound on Johnson's Algoritihm for Max-SAT. IEEE Conference on Computational Complexity 1997: 274-281
1995
1	EE	Hao Zheng, Kewal K. Saluja, Rajiv Jain: Test application time reduction for scan based sequential circuits. Great Lakes Symposium on VLSI 1995: 188-191

Coauthor Index

1	Jared Ahrens	[17]
2	Brandon M. Bachman	[4]
3	Wendy Belluomini	[6]
4	Jianer Chen	[2] [3]
5	Yifan Chen	[16]
6	Tiehua Du	[11]
7	Michael Epstein	[9]
8	Donald K. Friesen	[2] [3]
9	Ahmed Ginawi	[12]
10	Laszlo Hars	[9]
11	Geok Soon Hong	[11]
12	Rajiv Jain	[1]
13	Kip Kallpack	[6]
14	Raymond Krasinski	[9]
15	Jing Li	[12]
16	Billy Lim	[10]
17	Kah Bin Lim	[11]
18	Scott Little	[8] [14]
19	Eric Mercer (Eric G. Mercer)	[5] [7]
20	Di Mu	[15]
21	Chris J. Myers	[4] [5] [6] [7] [8] [14]
22	Eric Peskin	[6]
23	Martin Rosner	[9]
24	Kewal K. Saluja	[1]
25	Peilin Song	[13]
26	David Walter	[8] [14]
27	Xian Wu	[18]
28	Tian Xia	[12] [13] [15] [17]
29	Miao Xiong	[16]
30	Haiqiong Yao	[19]
31	Tomohiro Yoneda	[8] [14]
32	Wei Miao Yu	[11]
33	Yong Yu	[16] [18]

Colors in the list of coauthors