| |
| 2006 | ||
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| 3 | EE | S.-W. Tu, Y.-W. Chang, J.-Y. Jou: RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2258-2264 (2006) |
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| 2 | EE | R. Ernst, S. Sutarwala, J.-Y. Jou, M. Tong: Simulation based verification of register-transfer level behavioral synthesis tools. EURO-DAC 1990: 396-400 |
| 1989 | ||
| 1 | R. Ernst, S. Sutarwala, J.-Y. Jou: TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. ITC 1989: 937 | |
| 1 | Y.-W. Chang | [3] |
| 2 | R. Ernst | [1] [2] |
| 3 | S. Sutarwala | [1] [2] |
| 4 | M. Tong | [2] |
| 5 | S.-W. Tu | [3] |