Premachandran R. Menon

2006
43	EE	Premachandran R. Menon, Weifeng Xu, Russell Tessier: Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 867-877 (2006)
2001
42		Ian G. Harris, Premachandran R. Menon, Russell Tessier: BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938
41	EE	Ramesh C. Tekumalla, Premachandran R. Menon: Identification of primitive faults in combinational and sequentialcircuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1426-1442 (2001)
2000
40	EE	Ramesh C. Tekumalla, Premachandran R. Menon: On Redundant Path Delay Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 49(3): 277-282 (2000)
1999
39		Ramesh C. Tekumalla, Premachandran R. Menon: Robust testability of primitive faults using test points. ITC 1999: 260-268
1998
38	EE	Ramesh C. Tekumalla, Premachandran R. Menon: On primitive fault test generation in non-scan sequential circuits. ICCAD 1998: 275-282
1997
37	EE	Miron Abramovici, Premachandran R. Menon: Fault simulation on reconfigurable hardware. FCCM 1997: 182-191
36	EE	Ramesh C. Tekumalla, Premachandran R. Menon: Test generation for primitive path delay faults in combinational circuits. ICCAD 1997: 636-641
35		Ramesh C. Tekumalla, Premachandran R. Menon: Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD 1997: 648-653
34		Ramesh C. Tekumalla, Premachandran R. Menon: Delay Testing with Clock Control: An Alternative to Enhanced Scan. ITC 1997: 454-462
33	EE	Wolfgang Kunz, Dominik Stoffel, Premachandran R. Menon: Logic optimization and equivalence checking by implication analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 266-281 (1997)
1996
32	EE	Ramesh C. Tekumalla, Premachandran R. Menon: Identifying Redundant Path Delay Faults in Sequential Circuits. VLSI Design 1996: 406-411
1995
31	EE	Wuudiann Ke, Premachandran R. Menon: Multifault testability of delay-testable circuits. VTS 1995: 400-409
30		Wuudiann Ke, Premachandran R. Menon: Synthesis of Delay-Verifiable Combinational Circuits. IEEE Trans. Computers 44(2): 213-222 (1995)
29	EE	Wuudiann Ke, Premachandran R. Menon: Path-delay-fault testable nonscan sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 576-582 (1995)
28	EE	Wuudiann Ke, Premachandran R. Menon: Delay-testable implementations of symmetric functions. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 772-775 (1995)
27	EE	Wuudiann Ke, Premachandran R. Menon: Multifault and delay-fault testability of multilevel circuits. J. Electronic Testing 6(3): 333-336 (1995)
1994
26		Wuudiann Ke, Premachandran R. Menon: Synthesis of Delay-Verifiable Two-Level Circuits. EDAC-ETC-EUROASIC 1994: 297-301
25		Hitesh Ajuha, Premachandran R. Menon: Delay Reduction by Segment Substitution. EDAC-ETC-EUROASIC 1994: 82-86
24	EE	Wolfgang Kunz, Premachandran R. Menon: Multi-level logic optimization by implication analysis. ICCAD 1994: 6-13
23		Wuudiann Ke, Premachandran R. Menon: Delay-Verifiability of Combinational Circuits Based on Primitive Faults. ICCD 1994: 86-90
22	EE	Premachandran R. Menon, Hitesh Ahuja, Mohan Harihara: Redundancy identification and removal in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 646-651 (1994)
1993
21	EE	O. Y. Song, Bong-Hee Park, Premachandran R. Menon: Divergence and scheduling in functional level concurrent fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 734-736 (1993)
20	EE	Ohyoung Song, Premachandran R. Menon: Acceleration of trace-based fault simulation of combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1413-1419 (1993)
19	EE	Ohyoung Song, Premachandran R. Menon: 3-valued trace-based fault simulation of synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1419-1424 (1993)
1991
18		Bong-Hee Park, Premachandran R. Menon: Robustly Scan-Testable CMOS Sequential Circuits. ITC 1991: 263-272
17	EE	Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici: SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 738-747 (1991)
1989
16		C. H. Chen, Premachandran R. Menon: An Approach to Functional Level Testability Analysis. ITC 1989: 373-380
15		P. N. Anirudhan, Premachandran R. Menon: Symbolic Test Generation for Hierarchically Modeled Digital Systems. ITC 1989: 461-469
1986
14		Miron Abramovici, Premachandran R. Menon, David T. Miller: Checkpoint Faults are not Sufficient Target Faults for Test Generation. IEEE Trans. Computers 35(8): 769-771 (1986)
1985
13		Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller: Test Generation In Lamp2: System Overview. ITC 1985: 45-48
12		Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller: Test Generation In Lamp2: Concepts and Algorithms. ITC 1985: 49-56
11		Miron Abramovici, Premachandran R. Menon: A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. Computers 34(7): 658-663 (1985)
1983
10		Miron Abramovici, Premachandran R. Menon: A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. ITC 1983: 138-142
9		Gordon K. Lin, Premachandran R. Menon: Totally Preset Checking Experiments for Sequential Machines. IEEE Trans. Computers 32(2): 101-108 (1983)
8	EE	Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon: A Logic Simulation Machine. IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 82-94 (1983)
1982
7	EE	Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon: A logic simulation machine. ISCA 1982: 148-157
6		Ytzhak H. Levendel, Premachandran R. Menon: Test Generation Algorithms for Computer Hardware Description Languages. IEEE Trans. Computers 31(7): 577-588 (1982)
1978
5		Premachandran R. Menon, Stephen G. Chappell: Deductive Fault Simulation with Functional Blocks. IEEE Trans. Computers 27(8): 689-695 (1978)
1969
4		Premachandran R. Menon: On Sequential Machine Decompositions for Reducing the Number of Delay Elements Information and Control 15(3): 274-287 (1969)
3		Arthur D. Friedman, Premachandran R. Menon: Design of Generalized Double Rank and Multiple Rank Sequential Circuits Information and Control 15(5): 436-451 (1969)
1968
2		C. J. Tan, Premachandran R. Menon, Arthur D. Friedman: Structural Simplification and Decomposition of Asynchronous Sequential Circuits FOCS 1968: 7-19
1967
1		D. B. Armstrong, Arthur D. Friedman, Premachandran R. Menon: Synthesis of Asynchronous Sequential Circuits with Minimum Number of Delay Elements FOCS 1967: 95-105

Coauthor Index

1	Miron Abramovici	[7] [8] [10] [11] [12] [13] [14] [17] [37]
2	Hitesh Ahuja	[22]
3	Hitesh Ajuha	[25]
4	P. N. Anirudhan	[15]
5	D. B. Armstrong	[1]
6	Stephen G. Chappell	[5]
7	C. H. Chen	[16]
8	Arthur D. Friedman	[1] [2] [3]
9	Mohan Harihara	[22]
10	Ian G. Harris	[42]
11	Wuudiann Ke	[23] [26] [27] [28] [29] [30] [31]
12	James J. Kulikowski	[12] [13]
13	Wolfgang Kunz	[24] [33]
14	Ytzhak H. Levendel	[6] [7] [8] [17]
15	Gordon K. Lin	[9]
16	David T. Miller	[12] [13] [14]
17	Bong-Hee Park	[18] [21]
18	O. Y. Song	[21]
19	Ohyoung Song	[19] [20]
20	Dominik Stoffel	[33]
21	C. J. Tan	[2]
22	Ramesh C. Tekumalla	[32] [34] [35] [36] [38] [39] [40] [41]
23	Russell Tessier	[42] [43]
24	Weifeng Xu	[43]

Colors in the list of coauthors