| 2008 |
|---|
| 19 | EE | Kuang-Yao Lee,
Cheng-Kok Koh,
Ting-Chi Wang,
Kai-Yuan Chao:
Optimal post-routing redundant via insertion.
ISPD 2008: 111-117 |
| 18 | EE | Kuang-Yao Lee,
Cheng-Kok Koh,
Ting-Chi Wang,
Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008) |
| 17 | EE | Hua Xiang,
Kai-Yuan Chao,
Ruchir Puri,
Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008) |
| 16 | EE | Hua Xiang,
Liang Deng,
Ruchir Puri,
Kai-Yuan Chao,
Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008) |
| 2007 |
|---|
| 15 | EE | Liang Deng,
Martin D. F. Wong,
Kai-Yuan Chao,
Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography.
ASP-DAC 2007: 13-18 |
| 14 | EE | Hua Xiang,
Kai-Yuan Chao,
Ruchir Puri,
Martin D. F. Wong:
Is your layout density verification exact?: a fast exact algorithm for density calculation.
ISPD 2007: 19-26 |
| 13 | EE | Hua Xiang,
Liang Deng,
Ruchir Puri,
Kai-Yuan Chao,
Martin D. F. Wong:
Dummy fill density analysis with coupling constraints.
ISPD 2007: 3-10 |
| 2006 |
|---|
| 12 | EE | Kuang-Yao Lee,
Ting-Chi Wang,
Kai-Yuan Chao:
Post-routing redundant via insertion and line end extension with via density consideration.
ICCAD 2006: 633-640 |
| 11 | EE | Hua Xiang,
Kai-Yuan Chao,
Martin D. F. Wong:
An ECO routing algorithm for eliminating coupling-capacitance violations.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1754-1762 (2006) |
| 2005 |
|---|
| 10 | EE | Hua Xiang,
Kai-Yuan Chao,
Martin D. F. Wong:
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.
ISQED 2005: 181-186 |
| 2004 |
|---|
| 9 | EE | Hua Xiang,
Kai-Yuan Chao,
D. F. Wong:
An ECO algorithm for eliminating crosstalk violations.
ISPD 2004: 41-46 |
| 8 | EE | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou,
Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004) |
| 2002 |
|---|
| 7 | EE | Ruibing Lu,
Guoan Zhong,
Cheng-Kok Koh,
Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning.
DATE 2002: 690-695 |
| 6 | EE | Hua Xiang,
Kai-Yuan Chao,
D. F. Wong:
ECO algorithms for removing overlaps between power rails and signal wires.
ICCAD 2002: 67-74 |
| 1995 |
|---|
| 5 | EE | Kai-Yuan Chao,
D. F. Wong:
Signal integrity optimization on the pad assignment for high-speed VLSI design.
ICCAD 1995: 720-725 |
| 4 | EE | Kai-Yuan Chao,
D. F. Wong:
Thermal placement for high-performance multichip modules.
ICCD 1995: 218-223 |
| 3 | | Shashidhar Thakur,
Kai-Yuan Chao,
D. F. Wong:
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing.
ISCAS 1995: 207-210 |
| 2 | | Kai-Yuan Chao,
D. F. Wong:
Floorplanning for Low Power Designs.
ISCAS 1995: 45-48 |
| 1994 |
|---|
| 1 | EE | Kai-Yuan Chao,
D. F. Wong:
Layer assignment for high-performance multi-chip modules.
ICCAD 1994: 680-685 |
