| 2009 |
|---|
| 148 | EE | Smita Krishnaswamy,
Stephen Plaza,
Igor L. Markov,
John P. Hayes:
Signature-Based SER Analysis and Design of Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 74-86 (2009) |
| 2008 |
|---|
| 147 | EE | Smita Krishnaswamy,
Igor L. Markov,
John P. Hayes:
On the role of timing masking in reliable logic circuit design.
DAC 2008: 924-929 |
| 146 | EE | Sungsoon Cho,
John P. Hayes:
Optimizing router locations for minimum-energy wireless networks.
LCN 2008: 544-546 |
| 145 | EE | Smita Krishnaswamy,
George F. Viamontes,
Igor L. Markov,
John P. Hayes:
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 2007 |
|---|
| 144 | EE | Smita Krishnaswamy,
Stephen Plaza,
Igor L. Markov,
John P. Hayes:
Enhancing design robustness with reliability-aware resynthesis and logic simulation.
ICCAD 2007: 149-154 |
| 143 | EE | George F. Viamontes,
Igor L. Markov,
John P. Hayes:
Checking equivalence of quantum circuits and states.
ICCAD 2007: 69-74 |
| 142 | EE | Sungsoon Cho,
John P. Hayes:
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks.
LCN 2007: 403-410 |
| 141 | EE | John P. Hayes,
Ilia Polian,
Bernd Becker:
An Analysis Framework for Transient-Error Tolerance.
VTS 2007: 249-255 |
| 140 | EE | Smita Krishnaswamy,
Igor L. Markov,
John P. Hayes:
Tracking Uncertainty with Probabilistic Logic Circuit Testing.
IEEE Design & Test of Computers 24(4): 312-321 (2007) |
| 2006 |
|---|
| 139 | EE | Ramashis Das,
Igor L. Markov,
John P. Hayes:
On-Chip Test Generation Using Linear Subspaces.
European Test Symposium 2006: 111-116 |
| 138 | EE | Feng Gao,
John P. Hayes:
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2564-2571 (2006) |
| 137 | EE | Joonhwan Yi,
John P. Hayes:
High-level delay test generation for modular circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 576-590 (2006) |
| 136 | EE | Feng Gao,
John P. Hayes:
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction.
J. Low Power Electronics 2(2): 230-239 (2006) |
| 135 | EE | Aditya K. Prasad,
Vivek V. Shende,
Igor L. Markov,
John P. Hayes,
Ketan N. Patel:
Data structures and algorithms for simplifying reversible circuits.
JETC 2(4): 277-293 (2006) |
| 2005 |
|---|
| 134 | EE | Ilia Polian,
Thomas Fiehn,
Bernd Becker,
John P. Hayes:
A Family of Logical Fault Models for Reversible Circuits.
Asian Test Symposium 2005: 422-427 |
| 133 | EE | John P. Hayes:
Faults and Tests in Quantum Circuits.
Asian Test Symposium 2005 |
| 132 | EE | Feng Gao,
John P. Hayes:
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.
DAC 2005: 31-36 |
| 131 | EE | Smita Krishnaswamy,
George F. Viamontes,
Igor L. Markov,
John P. Hayes:
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices.
DATE 2005: 282-287 |
| 130 | EE | Nagarajan Kandasamy,
Sherif Abdelwahed,
Gregory C. Sharp,
John P. Hayes:
An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management.
Self-star Properties in Complex Information Systems 2005: 174-188 |
| 129 | EE | Nagarajan Kandasamy,
John P. Hayes,
Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis.
IEEE Trans. Parallel Distrib. Syst. 16(3): 258-270 (2005) |
| 128 | EE | Amit Chowdhary,
John P. Hayes:
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 999-1013 (2005) |
| 127 | EE | Joonhwan Yi,
John P. Hayes:
The Coupling Model for Function and Delay Faults.
J. Electronic Testing 21(6): 631-649 (2005) |
| 2004 |
|---|
| 126 | EE | John P. Hayes,
Ilia Polian,
Bernd Becker:
Testing for Missing-Gate Faults in Reversible Circuits.
Asian Test Symposium 2004: 100-105 |
| 125 | EE | George F. Viamontes,
Igor L. Markov,
John P. Hayes:
High-Performance QuIDD-Based Simulation of Quantum Circuits.
DATE 2004: 1354-1355 |
| 124 | EE | Rajesh Venkatasubramanian,
John P. Hayes:
Discovering 1-FT Routes in Mobile Ad Hoc Networks.
DSN 2004: 627-636 |
| 123 | EE | Nagarajan Kandasamy,
Sherif Abdelwahed,
John P. Hayes:
Self-Optimization in Computer Systems via On-Line Control: Application to Power Management.
ICAC 2004: 54-61 |
| 122 | EE | Feng Gao,
John P. Hayes:
Exact and heuristic approaches to input vector control for leakage power reduction.
ICCAD 2004: 527-532 |
| 121 | EE | Feng Gao,
John P. Hayes:
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction.
ICCD 2004: 258-264 |
| 120 | EE | Ketan N. Patel,
John P. Hayes,
Igor L. Markov:
Fault testing for reversible circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1220-1230 (2004) |
| 2003 |
|---|
| 119 | EE | John P. Hayes:
Tutorial: basic concepts in quantum circuits.
DAC 2003: 893 |
| 118 | EE | Rajesh Venkatasubramanian,
John P. Hayes,
Brian T. Murray:
Low-Cost On-Line Fault Detection Using Control Flow Assertions.
IOLTS 2003: 137-143 |
| 117 | EE | Feng Gao,
John P. Hayes:
ILP-based optimization of sequential circuits for low power.
ISLPED 2003: 140-145 |
| 116 | EE | Nagarajan Kandasamy,
John P. Hayes,
Brian T. Murray:
Dependable Communication Synthesis for Distributed Embedded Systems.
SAFECOMP 2003: 275-288 |
| 115 | EE | Ketan N. Patel,
John P. Hayes,
Igor L. Markov:
Fault Testing for Reversible Circuits.
VTS 2003: 410-416 |
| 114 | EE | Ronald D. Blanton,
John P. Hayes:
On the properties of the input pattern fault model.
ACM Trans. Design Autom. Electr. Syst. 8(1): 108-124 (2003) |
| 113 | EE | Vivek V. Shende,
Aditya K. Prasad,
Igor L. Markov,
John P. Hayes:
Synthesis of reversible logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 710-722 (2003) |
| 112 | EE | Feng Gao,
John P. Hayes:
On-Line Monitor Design of Finite-State Machines.
J. Electronic Testing 19(5): 537-548 (2003) |
| 2002 |
|---|
| 111 | EE | Nagarajan Kandasamy,
John P. Hayes,
Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems.
DSN 2002: 449-458 |
| 110 | EE | Vivek V. Shende,
Aditya K. Prasad,
Igor L. Markov,
John P. Hayes:
Reversible logic circuit synthesis.
ICCAD 2002: 353-360 |
| 109 | EE | Feng Gao,
John P. Hayes:
On-Line Monitor Design of Finite-State Machines.
IOLTW 2002: 74-78 |
| 108 | EE | John P. Hayes:
Fault-Tolerant Quantum Computers.
IPDPS 2002 |
| 107 | | Vivek V. Shende,
Aditya K. Prasad,
Igor L. Markov,
John P. Hayes:
Reversible Logic Circuit Synthesis.
IWLS 2002: 125-130 |
| 106 | EE | Amit Chowdhary,
John P. Hayes:
General technology mapping for field-programmable gate arrays based on lookup tables.
ACM Trans. Design Autom. Electr. Syst. 7(1): 1-32 (2002) |
| 105 | EE | Dimitris Nikolos,
John P. Hayes,
Michael Nicolaidis,
Cecilia Metra:
Guest Editorial.
J. Electronic Testing 18(3): 259-260 (2002) |
| 2001 |
|---|
| 104 | EE | Hakan Yalcin,
Robert Palermo,
Mohammad Mortazavi,
Cyrus Bamji,
Karem A. Sakallah,
John P. Hayes:
An Advanced Timing Characterization Method Using Mode Dependency.
DAC 2001: 657-660 |
| 103 | EE | Hyungwon Kim,
John P. Hayes:
Delay fault testing of IP-based designs via symbolic path modeling.
IEEE Trans. VLSI Syst. 9(5): 661-678 (2001) |
| 102 | EE | Hyungwon Kim,
John P. Hayes:
Realization-independent ATPG for designs with unimplemented blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 290-306 (2001) |
| 101 | EE | Hakan Yalcin,
Mohammad Mortazavi,
Robert Palermo,
Cyrus Bamji,
Karem A. Sakallah,
John P. Hayes:
Fast and accurate timing characterization using functionalinformation.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 315-331 (2001) |
| 2000 |
|---|
| 100 | EE | Hussain Al-Asaad,
John P. Hayes:
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits.
VTS 2000: 221-230 |
| 99 | EE | Avaneendra Gupta,
John P. Hayes:
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells.
ACM Trans. Design Autom. Electr. Syst. 5(3): 510-547 (2000) |
| 98 | EE | David Van Campenhout,
Trevor N. Mudge,
John P. Hayes:
Collection and Analysis of Microprocessor Design Errors.
IEEE Design & Test of Computers 17(4): 51-60 (2000) |
| 97 | EE | Ronald D. Blanton,
John P. Hayes:
On the design of fast, easily testable ALU's.
IEEE Trans. VLSI Syst. 8(2): 220-223 (2000) |
| 96 | EE | Hussain Al-Asaad,
John P. Hayes:
Logic Design Validation via Simulation and Automatic Test Pattern Generation.
J. Electronic Testing 16(6): 575-589 (2000) |
| 1999 |
|---|
| 95 | EE | David Van Campenhout,
Trevor N. Mudge,
John P. Hayes:
High-Level Test Generation for Design Verification of Pipelined Microprocessors.
DAC 1999: 185-188 |
| 94 | | Hyungwon Kim,
John P. Hayes:
Delay fault testing of IP-based designs via symbolic path modeling.
ITC 1999: 1045-1054 |
| 93 | EE | Nagarajan Kandasamy,
John P. Hayes,
Brian T. Murray:
Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems.
SRDS 1999: 212-221 |
| 92 | EE | Avaneendra Gupta,
John P. Hayes:
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells.
VLSI Design 1999: 453-459 |
| 91 | EE | Hyungwon Kim,
John P. Hayes:
Delay Fault Testing of Designs with Embedded IP Cores.
VTS 1999: 160-167 |
| 90 | EE | Mark C. Hansen,
Hakan Yalcin,
John P. Hayes:
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering.
IEEE Design & Test of Computers 16(3): 72-80 (1999) |
| 1998 |
|---|
| 89 | EE | Avaneendra Gupta,
John P. Hayes:
Optimal 2-D cell layout with integrated transistor folding.
ICCAD 1998: 128-135 |
| 88 | EE | Hyungwon Kim,
John P. Hayes:
High-coverage ATPG for datapath circuits with unimplemented blocks.
ITC 1998: 577-586 |
| 87 | EE | David Van Campenhout,
Hussain Al-Asaad,
John P. Hayes,
Trevor N. Mudge,
Richard B. Brown:
High-level design verification of microprocessors via error modeling.
ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998) |
| 86 | EE | Hussain Al-Asaad,
Brian T. Murray,
John P. Hayes:
Online BIST for Embedded Systems.
IEEE Design & Test of Computers 15(4): 17-24 (1998) |
| 85 | | Krishnendu Chakrabarty,
Brian T. Murray,
John P. Hayes:
Optimal Zero-Aliasing Space Compaction of Test Responses.
IEEE Trans. Computers 47(11): 1171-1187 (1998) |
| 84 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Zero-aliasing space compaction of test responses using multiple parity signatures.
IEEE Trans. VLSI Syst. 6(2): 309-313 (1998) |
| 83 | EE | Hussain Al-Asaad,
John P. Hayes,
Brian T. Murray:
Scalable Test Generators for High-Speed Datapath Circuits.
J. Electronic Testing 12(1-2): 111-125 (1998) |
| 1997 |
|---|
| 82 | EE | Avaneendra Gupta,
John P. Hayes:
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells.
DAC 1997: 452-455 |
| 81 | EE | Ronald D. Blanton,
John P. Hayes:
The input pattern fault model and its application.
ED&TC 1997: 628 |
| 80 | EE | Amit Chowdhary,
John P. Hayes:
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs.
FPGA 1997: 43-49 |
| 79 | | Ronald D. Blanton,
John P. Hayes:
Properties of the Input Pattern Fault Model.
ICCD 1997: 372-380 |
| 78 | | Avaneendra Gupta,
John P. Hayes:
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells.
VLSI Design 1997: 15-20 |
| 77 | EE | Hakan Yalcin,
John P. Hayes:
Event propagation conditions in circuit delay computation.
ACM Trans. Design Autom. Electr. Syst. 2(3): 249-280 (1997) |
| 76 | | Hung-Kuei Ku,
John P. Hayes:
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses.
IEEE Trans. Computers 46(4): 439-455 (1997) |
| 75 | EE | Hung-Kuei Ku,
John P. Hayes:
Connective Fault Tolerance in Multiple-Bus Systems.
IEEE Trans. Parallel Distrib. Syst. 8(6): 574-586 (1997) |
| 74 | EE | Krishnendu Chakrabarty,
John P. Hayes:
On the quality of accumulator-based compaction of test responses.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 916-922 (1997) |
| 73 | EE | R. D. (Shawn) Blanton,
John P. Hayes:
Testability Properties of Divergent Trees.
J. Electronic Testing 11(3): 197-209 (1997) |
| 1996 |
|---|
| 72 | EE | Hakan Yalcin,
John P. Hayes,
Karem A. Sakallah:
An approximate timing analysis method for datapath circuits.
ICCAD 1996: 114-118 |
| 71 | EE | Avaneendra Gupta,
John P. Hayes:
Width minimization of two-dimensional CMOS cells using integer programming.
ICCAD 1996: 660-667 |
| 70 | EE | R. D. (Shawn) Blanton,
John P. Hayes:
Design of a fast, easily testable ALU.
VTS 1996: 9-16 |
| 69 | | Brian T. Murray,
John P. Hayes:
Testing ICs: Getting to the Core of the Problem.
IEEE Computer 29(11): 32-38 (1996) |
| 68 | | Ronald D. Blanton,
John P. Hayes:
Testability of Convergent Tree Circuits.
IEEE Trans. Computers 45(8): 950-963 (1996) |
| 67 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Test response compaction using multiplexed parity trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1399-1408 (1996) |
| 66 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Balance testing and balance-testable design of logic circuits.
J. Electronic Testing 8(1): 71-86 (1996) |
| 65 | EE | Frank Harary,
John P. Hayes:
Node fault tolerance in graphs.
Networks 27(1): 19-23 (1996) |
| 64 | EE | Hung-Kuei Ku,
John P. Hayes:
Optimally edge fault-tolerant trees.
Networks 27(3): 203-214 (1996) |
| 1995 |
|---|
| 63 | EE | Hussain Al-Asaad,
John P. Hayes:
Design verification via simulation and automatic test pattern generation.
ICCAD 1995: 174-180 |
| 62 | EE | Amit Chowdhary,
John P. Hayes:
Technology mapping for field-programmable gate arrays using integer programming.
ICCAD 1995: 346-352 |
| 61 | EE | Hakan Yalcin,
John P. Hayes:
Hierarchical timing analysis using conditional delays.
ICCAD 1995: 371-377 |
| 60 | | Mark C. Hansen,
John P. Hayes:
High-Level Test Generation Using Symbolic Scheduling.
ITC 1995: 586-595 |
| 59 | | Krishnendu Chakrabarty,
Brian T. Murray,
John P. Hayes:
Optimal Space Compaction of Test Responses.
ITC 1995: 834-843 |
| 58 | EE | Mark C. Hansen,
John P. Hayes:
High-level test generation using physically-induced faults.
VTS 1995: 20-28 |
| 57 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Cumulative balance testing of logic circuits.
IEEE Trans. VLSI Syst. 3(1): 72-83 (1995) |
| 1994 |
|---|
| 56 | EE | Krishnendu Chakrabarty,
John P. Hayes:
DFBT: A Design-for-Testability Method Based on Balance Testing.
DAC 1994: 351-357 |
| 55 | | Hung-Kuei Ku,
John P. Hayes:
Connectivity and Fault Tolerance of Multiple-Bus Systems.
FTCS 1994: 372-381 |
| 54 | | Krishnendu Chakrabarty,
John P. Hayes:
Efficient Test-Response Compression for Multiple-Output Cicuits.
ITC 1994: 501-510 |
| 1993 |
|---|
| 53 | | Ronald D. Blanton,
John P. Hayes:
Efficient Testing of Tree Circuits.
FTCS 1993: 176-185 |
| 52 | | Krishnendu Chakrabarty,
John P. Hayes:
Balance Testing of Logic Circuits.
FTCS 1993: 350-359 |
| 51 | | Pinaki Mazumder,
John P. Hayes:
Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories.
IEEE Design & Test of Computers 10(1): 6-7 (1993) |
| 50 | | Ram Raghavan,
John P. Hayes:
Reducing Inerference Among Vector Accesses in Interleaved Memories.
IEEE Trans. Computers 42(4): 471-483 (1993) |
| 1992 |
|---|
| 49 | EE | Michael J. Batek,
John P. Hayes:
Test-Set Preserving Logic Transformations.
DAC 1992: 454-458 |
| 48 | | Tze Chiang Lee,
John P. Hayes:
A Fault-Tolerant Communication Scheme for Hypercube Computers.
IEEE Trans. Computers 41(10): 1242-1256 (1992) |
| 47 | | Shantanu Dutt,
John P. Hayes:
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors.
IEEE Trans. Computers 41(5): 588-598 (1992) |
| 46 | EE | Eduard Cerny,
John P. Hayes,
Nicholas C. Rumin:
Accuracy of magnitude-class calculations in switch-level modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 443-452 (1992) |
| 45 | | Tze Chiang Lee,
John P. Hayes:
Design of Gracefully Degradable Hypercube-Connected Systems.
J. Parallel Distrib. Comput. 14(4): 390-401 (1992) |
| 1991 |
|---|
| 44 | EE | Robert L. Maziasz,
John P. Hayes:
Exact Width and Height Minimization of CMOS Cells.
DAC 1991: 487-493 |
| 43 | | Shantanu Dutt,
John P. Hayes:
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors.
FTCS 1991: 292-299 |
| 42 | | Ram Raghavan,
John P. Hayes:
Scalar-Vector Memory Interference in Vector Computers.
ICPP (1) 1991: 180-187 |
| 41 | | Brian T. Murray,
John P. Hayes:
Test Propagation Through Modules and Circuits.
ITC 1991: 748-757 |
| 40 | | Shantanu Dutt,
John P. Hayes:
Subcube Allocation in Hypercube Computers.
IEEE Trans. Computers 40(3): 341-352 (1991) |
| 39 | | Shantanu Dutt,
John P. Hayes:
Designing Fault-Tolerant System Using Automorphisms.
J. Parallel Distrib. Comput. 12(3): 249-268 (1991) |
| 1990 |
|---|
| 38 | EE | Ram Raghavan,
John P. Hayes:
On randomly interleaved memories.
SC 1990: 49-58 |
| 37 | | Shantanu Dutt,
John P. Hayes:
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures.
IEEE Trans. Computers 39(4): 490-503 (1990) |
| 36 | EE | Brian T. Murray,
John P. Hayes:
Hierarchical test generation using precomputed tests for modules.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 594-603 (1990) |
| 35 | EE | Robert L. Maziasz,
John P. Hayes:
Layout optimization of static CMOS functional cells.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 708-719 (1990) |
| 34 | EE | Debashis Bhattacharya,
John P. Hayes:
Designing for high-level test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 752-766 (1990) |
| 33 | EE | Debashis Bhattacharya,
John P. Hayes:
A hierarchical test generation methodology for digital circuits.
J. Electronic Testing 1(2): 103-123 (1990) |
| 1989 |
|---|
| 32 | | Debashis Bhattacharya,
Brian T. Murray,
John P. Hayes:
High-Level Test Generation for VLSI.
IEEE Computer 22(4): 16-24 (1989) |
| 1988 |
|---|
| 31 | | Brian T. Murray,
John P. Hayes:
Hierarchical Test Generation Using Precomputed Tests for Modules.
ITC 1988: 221-229 |
| 30 | | Raif M. Yanney,
John P. Hayes:
Fault Recovery in Distributed Processing Loop Networks.
Computer Networks 15: 229-243 (1988) |
| 29 | EE | Y. You,
John P. Hayes:
Implementation of VLSI self-testing by regularization.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1261-1271 (1988) |
| 28 | EE | Musaravakkam S. Krishnan,
John P. Hayes:
A normalized-area measure for VLSI layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 411-419 (1988) |
| 1987 |
|---|
| 27 | EE | R. L. Maiasz,
John P. Hayes:
Layout Optimization of CMOS Functional Cells.
DAC 1987: 544-551 |
| 1986 |
|---|
| 26 | | John P. Hayes,
Trevor N. Mudge,
Quentin F. Stout:
Architecture of a Hypercube Supercomputer.
ICPP 1986: 653-660 |
| 25 | | Raif M. Yanney,
John P. Hayes:
Distributed Recovery in Fault-Tolerant Multiprocessor Networks.
IEEE Trans. Computers 35(10): 871-879 (1986) |
| 24 | | Musaravakkam S. Krishnan,
John P. Hayes:
An Array Layout Methodology for VLlSI Circuits.
IEEE Trans. Computers 35(12): 1055-1067 (1986) |
| 23 | | John P. Hayes:
Uncertainty, Energy, and Multiple-Valued Logics.
IEEE Trans. Computers 35(2): 107-114 (1986) |
| 22 | | John P. Hayes:
Pseudo-Boolean Logic Circuits.
IEEE Trans. Computers 35(7): 602-612 (1986) |
| 21 | EE | John P. Hayes:
Digital Simulation with Multiple Logic Values.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(2): 274-283 (1986) |
| 20 | | Trevor N. Mudge,
John P. Hayes,
Gregory D. Buzzard,
Donald C. Winsor:
Analysis of Multiple-Bus Interconnection Networks.
J. Parallel Distrib. Comput. 3(3): 328-343 (1986) |
| 19 | EE | John Paul Shen,
John P. Hayes,
Luigi Ciminiera,
Angelo Serra:
Fault-tolerance and performance analysis of beta-networks.
Parallel Computing 3(3): 231-249 (1986) |
| 1984 |
|---|
| 18 | | Raif M. Yanney,
John P. Hayes:
Distributed Recovery in Fault-Tolerant Multiprocessor Networks.
ICDCS 1984: 514-525 |
| 17 | | John Paul Shen,
John P. Hayes:
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks.
IEEE Trans. Computers 33(3): 241-248 (1984) |
| 16 | EE | John P. Hayes:
Fault Modeling for Digital MOS Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 200-208 (1984) |
| 1981 |
|---|
| 15 | | Thirumalai Sridhar,
John P. Hayes:
Design of Easily Testable Bit-Sliced Systems.
IEEE Trans. Computers 30(11): 842-854 (1981) |
| 14 | | Thirumalai Sridhar,
John P. Hayes:
A Functional Approach to Testing Bit-Sliced Microprocessors.
IEEE Trans. Computers 30(8): 563-571 (1981) |
| 1980 |
|---|
| 13 | | John Paul Shen,
John P. Hayes:
Fault Tolerance of a Class of Connecting Networks.
ISCA 1980: 61-71 |
| 12 | | Ayee Goundan,
John P. Hayes:
Design of Totally Fault Locatable Combinational Networks.
IEEE Trans. Computers 29(1): 33-44 (1980) |
| 11 | | Ayee Goundan,
John P. Hayes:
Identification of Equivalent Faults in Logic Networks.
IEEE Trans. Computers 29(11): 978-985 (1980) |
| 10 | | John P. Hayes:
Testing Memories for Single-Cell Pattern-Sensitive Faults.
IEEE Trans. Computers 29(3): 249-254 (1980) |
| 1978 |
|---|
| 9 | | John P. Hayes:
Generation of Optimal Transition Count Tests.
IEEE Trans. Computers 27(1): 36-41 (1978) |
| 8 | | John P. Hayes:
Path Complexity of Logic Networks.
IEEE Trans. Computers 27(5): 459-462 (1978) |
| 1976 |
|---|
| 7 | | John P. Hayes:
Transition Count Testing of Combinational Logic Circuits.
IEEE Trans. Computers 25(6): 613-620 (1976) |
| 6 | | John P. Hayes:
A Graph Model for Fault-Tolerant Computing Systems.
IEEE Trans. Computers 25(9): 875-884 (1976) |
| 5 | | John P. Hayes:
On the Properties of Irredundant Logic Networks.
IEEE Trans. Computers 25(9): 884-892 (1976) |
| 4 | EE | John P. Hayes:
Enumeration of Fanout-Free Boolean Functions.
J. ACM 23(4): 700-709 (1976) |
| 1975 |
|---|
| 3 | | John P. Hayes:
Detection of Pattern-Sensitive Faults in Random-Access Memories.
IEEE Trans. Computers 24(2): 150-157 (1975) |
| 2 | EE | John P. Hayes:
The Fanout Structure of Switching Functions.
J. ACM 22(4): 551-571 (1975) |
| 1974 |
|---|
| 1 | | John P. Hayes:
Minimization of Fanout in Switching Networks
FOCS 1974: 133-139 |
