2008 | ||
---|---|---|
60 | EE | Ruiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong: Static timing: Back to our roots. ASP-DAC 2008: 310-315 |
59 | EE | Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah: Incremental Criticality and Yield Gradients. DATE 2008: 1130-1135 |
58 | EE | Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah, Peter A. Habitz: Optimal Margin Computation for At-Speed Test. DATE 2008: 622-627 |
57 | EE | Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah: Statistical path selection for at-speed test. ICCAD 2008: 624-631 |
56 | EE | Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah: Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. PATMOS 2008: 178-187 |
2007 | ||
55 | EE | Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah: Variation-aware performance verification using at-speed structural test and statistical timing. ICCAD 2007: 405-412 |
54 | EE | Vladimir Zolotov, Jinjun Xiong, S. Abbaspour, David J. Hathaway, Chandu Visweswariah: Compact modeling of variational waveforms. ICCAD 2007: 705-712 |
53 | EE | Jinjun Xiong, Vladimir Zolotov, Lei He: Robust Extraction of Spatial Correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 619-631 (2007) |
2006 | ||
52 | EE | Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah: Criticality computation in parameterized statistical timing. DAC 2006: 63-68 |
51 | EE | Jinjun Xiong, Vladimir Zolotov, Lei He: Robust extraction of spatial correlation. ISPD 2006: 2-9 |
50 | EE | Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Optimal placement of power-supply pads and pins. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 144-154 (2006) |
49 | EE | Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda: Impact of stress-induced backflow on full-chip electromigration risk assessment. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1038-1046 (2006) |
2005 | ||
48 | EE | Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown: Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI 2005: 313-316 |
47 | EE | Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324 |
46 | EE | Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah: Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. DAC 2005: 71-76 |
45 | Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov: Gate sizing using incremental parameterized statistical timing analysis. ICCAD 2005: 1029-1036 | |
44 | Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712 | |
43 | Amit Jain, David Blaauw, Vladimir Zolotov: Accurate delay computation for noisy waveform shapes. ICCAD 2005: 947-953 | |
42 | Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh: Pessimism reduction in crosstalk noise aware STA. ICCAD 2005: 954-961 | |
2004 | ||
41 | EE | Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Optimal placement of power supply pads and pins. DAC 2004: 165-170 |
40 | EE | Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176 |
39 | EE | Dongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. DAC 2004: 664-669 |
38 | EE | Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer: False-Noise Analysis for Domino Circuits. DATE 2004: 784-789 |
37 | EE | Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda: Delay noise pessimism reduction by logic correlations. ICCAD 2004: 160-167 |
36 | EE | Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda: A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. ISQED 2004: 232-237 |
35 | EE | Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004) |
34 | EE | Aseem Agarwal, Vladimir Zolotov, David Blaauw: Statistical clock skew analysis considering intradie-process variations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004) |
2003 | ||
33 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353 |
32 | EE | Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957 |
31 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067 |
30 | EE | D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128 |
29 | EE | Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192 |
28 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. ICCAD 2003: 900-907 |
27 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Clock Skew Analysis Considering Intra-Die Process Variations. ICCAD 2003: 914-921 |
26 | EE | Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671 |
25 | EE | Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176 |
24 | EE | Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377- |
23 | EE | David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta: Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003) |
22 | EE | Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003) |
21 | EE | Aseem Agarwal, Vladimir Zolotov, David T. Blaauw: Statistical timing analysis using bounds and selective enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003) |
2002 | ||
20 | EE | Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-464 |
19 | EE | Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227 |
18 | EE | Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594 |
17 | EE | Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430 |
16 | EE | Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437- |
15 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21 |
14 | EE | Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal: Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 22-28 |
13 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36 |
12 | EE | Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov: False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002) |
11 | EE | Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002) |
10 | EE | David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran: Slope propagation in static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1180-1195 (2002) |
2001 | ||
9 | EE | Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao: Inductance 101: Analysis and Design Issues. DAC 2001: 329-334 |
8 | EE | Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo: Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725 |
7 | EE | Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov: False-Noise Analysis using Logic Implications. ICCAD 2001: 515- |
6 | EE | Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158- |
2000 | ||
5 | EE | David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80 |
4 | EE | Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov: ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238 |
3 | EE | Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68 |
2 | David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343 | |
1 | EE | Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184 |