2009 |
39 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Axel Poschmann,
Johann Großschädl,
Frank K. Gürkaynak,
Marco Macchetti,
Zeynep Toprak Deniz,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Transactions on Computational Science 4: 230-243 (2009) |
2008 |
38 | EE | Paolo Bonzini,
Giovanni Ansaloni,
Laura Pozzi:
Compiling custom instructions onto expression-grained reconfigurable architectures.
CASES 2008: 51-60 |
37 | EE | Giovanni Ansaloni,
Paolo Bonzini,
Laura Pozzi:
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays.
SASP 2008: 26-33 |
36 | EE | Paolo Bonzini,
Laura Pozzi:
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors.
IEEE Trans. VLSI Syst. 16(10): 1259-1267 (2008) |
2007 |
35 | EE | Paolo Bonzini,
Laura Pozzi:
A Retargetable Framework for Automated Discovery of Custom Instructions.
ASAP 2007: 334-341 |
34 | EE | Laura Pozzi,
Pierre G. Paulin:
A future of customizable processors: are we there yet?
DATE 2007: 1224-1225 |
33 | EE | Paolo Bonzini,
Laura Pozzi:
Polynomial-time subgraph enumeration for automated instruction set extension.
DATE 2007: 1331-1336 |
32 | EE | Francesco Regazzoni,
Stéphane Badel,
Thomas Eisenbarth,
Johann Großschädl,
Axel Poschmann,
Zeynep Toprak Deniz,
Marco Macchetti,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS 2007: 209-214 |
31 | EE | Paolo Bonzini,
Dilek Harmanci,
Laura Pozzi:
A Study of Energy Saving in Customizable Processors.
SAMOS 2007: 304-312 |
30 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
CoRR abs/0710.4820: (2007) |
29 | EE | Partha Biswas,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007) |
2006 |
28 | EE | Paolo Bonzini,
Laura Pozzi:
Code transformation strategies for extensible embedded processors.
CASES 2006: 242-252 |
27 | EE | Partha Biswas,
Nikil D. Dutt,
Paolo Ienne,
Laura Pozzi:
Automatic identification of application-specific functional units with architecturally visible storage.
DATE 2006: 212-217 |
26 | EE | Johann Großschädl,
Paolo Ienne,
Laura Pozzi,
Stefan Tillich,
Ajay K. Verma:
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.
DATE 2006: 218-223 |
25 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Paolo Ienne,
Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
VLSI Design 2006: 651-656 |
24 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. VLSI Syst. 14(7): 754-762 (2006) |
23 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors.
IEEE Trans. VLSI Syst. 14(8): 910-915 (2006) |
22 | EE | Laura Pozzi,
Kubilay Atasu,
Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1209-1229 (2006) |
21 | EE | André DeHon,
Yury Markovskiy,
Eylon Caspi,
Michael Chu,
Randy Huang,
Stylianos Perissakis,
Laura Pozzi,
Joseph Yeh,
John Wawrzynek:
Stream computations organized for reconfigurable execution.
Microprocessors and Microsystems 30(6): 334-354 (2006) |
2005 |
20 | EE | Laura Pozzi,
Paolo Ienne:
Exploiting pipelining to relax register-file port constraints of instruction-set extensions.
CASES 2005: 2-10 |
19 | EE | Miljan Vuletic,
Christophe Dubach,
Laura Pozzi,
Paolo Ienne:
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.
CODES+ISSS 2005: 243-248 |
18 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
DATE 2005: 1246-1251 |
17 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Seamless Hardware-Software Integration in Reconfigurable Computing Systems.
IEEE Design & Test of Computers 22(2): 102-113 (2005) |
2004 |
16 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.
ASAP 2004: 339-351 |
15 | EE | Partha Biswas,
Vinay Choudhary,
Kubilay Atasu,
Laura Pozzi,
Paolo Ienne,
Nikil Dutt:
Introduction of local memory elements in instruction set extensions.
DAC 2004: 729-734 |
14 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors.
DAC 2004: 948-953 |
13 | EE | Miljan Vuletic,
Ludovic Righetti,
Laura Pozzi,
Paolo Ienne:
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.
DATE 2004: 748 |
12 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.
FCCM 2004: 24-33 |
11 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.
FPL 2004: 596-605 |
10 | EE | Diviya Jain,
Anshul Kumar,
Laura Pozzi,
Paolo Ienne:
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.
SCOPES 2004: 17-32 |
2003 |
9 | EE | Armita Peymandoust,
Laura Pozzi,
Paolo Ienne,
Giovanni De Micheli:
Automatic Instruction Set Extension and Utilization for Embedded Processors.
ASAP 2003: 108- |
8 | EE | Kubilay Atasu,
Laura Pozzi,
Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints.
DAC 2003: 256-261 |
7 | EE | Kubilay Atasu,
Laura Pozzi,
Paolo Ienne:
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.
International Journal of Parallel Programming 31(6): 411-428 (2003) |
2002 |
6 | EE | Laura Pozzi,
Miljan Vuletic,
Paolo Ienne:
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors.
DATE 2002: 1138 |
2001 |
5 | EE | Cesare Alippi,
William Fornaciari,
Laura Pozzi,
Mariagiovanna Sami:
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
IEEE International Workshop on Rapid System Prototyping 2001: 50-57 |
2000 |
4 | EE | Cesare Alippi,
William Fornaciari,
Laura Pozzi,
Mariagiovanna Sami:
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
FPGA 2000: 218 |
1999 |
3 | EE | Cesare Alippi,
William Fornaciari,
Laura Pozzi,
Mariagiovanna Sami:
A DAG-Based Design Approach for Reconfigurable VLIW Processors.
DATE 1999: 778-779 |
1998 |
2 | EE | Franco Fummi,
A. Marshall,
Laura Pozzi,
Mariagiovanna Sami:
Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract).
FPGA 1998: 258 |
1997 |
1 | EE | Fabrizio Ferrandi,
Franco Fummi,
Laura Pozzi,
Mariagiovanna Sami:
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays.
DFT 1997: 85-93 |