George A. Constantinides

2009
64	EE	Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung: Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144
63	EE	Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator. ARC 2009: 231-242
62	EE	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 305-315 (2009)
61	EE	Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung: Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. TRETS 1(4): (2009)
2008
60	EE	Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135
59	EE	Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A Parallel Hardware Architecture for Image Feature Detection. ARC 2008: 136-147
58	EE	Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. ARC 2008: 231-242
57	EE	Antonio Roldao Lopes, George A. Constantinides: A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. ARC 2008: 75-86
56	EE	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184
55	EE	David Boland, George A. Constantinides: An FPGA-based implementation of the MINRES algorithm. FPL 2008: 379-384
54	EE	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith: Glitch-aware output switching activity from word-level statistics. ISCAS 2008: 1792-1795
53	EE	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. VLSI Syst. 16(6): 733-744 (2008)
52	EE	George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong: Guest Editorial: Field Programmable Technology. Signal Processing Systems 51(1): 1-2 (2008)
2007
51	EE	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260
50	EE	Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318
49	EE	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: On the feasibility of early routing capacitance estimation for FPGAs. FPL 2007: 234-239
48	EE	Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL 2007: 576-579
47	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007)
2006
46	EE	Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216
45	EE	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM 2006: 275-276
44	EE	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100
43	EE	Su-Shin Ang, George A. Constantinides: Dynamic Memory Sub-System for Reconfigurable Platforms. FPL 2006: 1-2
42	EE	Jonathan A. Clarke, George A. Constantinides: High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. FPL 2006: 1-2
41	EE	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL 2006: 1-6
40	EE	Konstantinos Masselos, George A. Constantinides, Qiang Liu: Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. FPL 2006: 1-6
39	EE	Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Leong: FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. FPL 2006: 1-6
38	EE	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6
37	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176
36	EE	Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung: Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS 2006
35	EE	George A. Constantinides: Word-length optimization for differentiable nonlinear systems. ACM Trans. Design Autom. Electr. Syst. 11(1): 26-43 (2006)
34	EE	Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides: Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1990-2000 (2006)
2005
33	EE	Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM 2005: 13-22
32	EE	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148
31	EE	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA 2005: 268
30		Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Power and Area Optimization for Multiple Restricted Multiplication. FPL 2005: 112-117
29		Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL 2005: 124-129
28		Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Heterogeneity Exploration for Multiple 2D Filter Designs. FPL 2005: 263-268
27		Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides: FPGA-Accelerated Reconstruction of Gene Regulatory Networks. FPL 2005: 323-328
26		Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL 2005: 341-346
25		Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414
24		Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides: Parameterized Logic Power Consumption Models for FPGA based Systems. FPL 2005: 626-629
23		Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL 2005: 77-82
22	EE	Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A novel 2D filter design methodology. ISCAS (1) 2005: 532-535
21	EE	Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: A heuristic approach for multiple restricted multiplication. ISCAS (1) 2005: 692-695
20	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. VLSI Syst. 13(1): 39-57 (2005)
2004
19	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272
18	EE	George A. Constantinides, Abunaser Miah, Nalin Sidahao: Word-Length Optimization of Folded Polynomial Evaluation. FCCM 2004: 285-286
17	EE	Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Migrating Functionality from ROMS to Embedded Multipliers. FCCM 2004: 287-288
16	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051
15	EE	Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL 2004: 200-208
14	EE	Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Multiple Restricted Multiplication. FPL 2004: 374-383
13	EE	Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa: Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004)
2003
12		Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings Springer 2003
11	EE	George A. Constantinides: Perturbation Analysis for Word-length Optimization. FCCM 2003: 81-90
10	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615
9	EE	Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Architectures for function evaluation on FPGAs. ISCAS (2) 2003: 804-807
8	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003)
7	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Wordlength optimization for linear digital signal processing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1432-1442 (2003)
2002
6	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum Wordlength Allocation. FCCM 2002: 219-228
5	EE	George A. Constantinides, Gerhard J. Woeginger: The complexity of multiple wordlength assignment. Appl. Math. Lett. 15(2): 137-140 (2002)
2001
4	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797
2000
3	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple Precision for Resource Minimization. FCCM 2000: 307-308
2	EE	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple-Wordlength Resource Binding. FPL 2000: 646-655
1999
1		George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332

Coauthor Index

1	Su-Shin Ang	[43] [46] [50]
2	Maria E. Angelopoulou	[60]
3	David Boland	[55]
4	Vanderlei Bonato	[48] [59]
5	Christos-Savvas Bouganis	[22] [27] [28] [33] [58] [60] [61] [63]
6	Nicola Campregher	[25] [32] [38] [44]
7	Peter Y. K. Cheung	[1] [2] [3] [4] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [17] [19] [20] [21] [22] [23] [25] [26] [28] [29] [30] [31] [32] [33] [36] [37] [38] [41] [44] [45] [46] [47] [49] [50] [51] [53] [54] [56] [60] [61] [62] [64]
8	Ray C. C. Cheung	[34]
9	Jonathan A. Clarke	[24] [36] [42] [49] [54]
10	Chun Te Ewe	[15] [29]
11	Altaf Abdul Gaffar	[24] [34] [36]
12	Asma Kahoul	[64]
13	Dong-U Lee	[34]
14	Philip Leong	[39]
15	Qiang Liu	[40] [51] [56] [62]
16	Antonio Roldao Lopes	[57]
17	Wayne Luk	[1] [2] [3] [4] [6] [7] [8] [10] [16] [19] [20] [34] [37] [46] [47] [50]
18	Wai-Kei Mak	[52]
19	Eduardo Marques	[48] [59]
20	Kostas Masselos (Konstantinos Masselos)	[39] [40] [51] [56] [62]
21	Oskar Mencer	[34]
22	Abunaser Miah	[18]
23	Gareth W. Morris	[17] [23]
24	Sung-Boem Park	[61]
25	Iosifina Pournara	[27]
26	Chalermpol Saiprasert	[58] [63]
27	N. Pete Sedcole	[10] [16] [19] [37] [47]
28	Nalin Sidahao	[9] [14] [18] [21] [30]
29	Alastair M. Smith	[26] [31] [41] [45] [53] [54] [64]
30	José T. de Sousa	[12] [13]
31	Kieron Turkington	[39]
32	Milan Vasilko	[25] [32] [38] [44]
33	Theerayod Wiangtong	[52]
34	Gerhard J. Woeginger	[5]

Colors in the list of coauthors