Jwu E. Chen

2007
43	EE	Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1625-1636 (2007)
42	EE	Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electronic Testing 23(4): 341-355 (2007)
2006
41	EE	Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen: IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371
40	EE	Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen: IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2513-2525 (2006)
2005
39	EE	Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187
38	EE	Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium 2005: 224-229
37	EE	Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium 2005: 324-329
36	EE	Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen: Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365
35	EE	Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen: Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36
2004
34	EE	Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150
33	EE	Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen: A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium 2004: 58-61
2003
32	EE	Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19(4): 637-651 (2003)
2002
31	EE	Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen: A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium 2002: 170-175
30	EE	Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen: An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE 2002: 1119
29	EE	Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electronic Testing 18(6): 571-581 (2002)
2001
28	EE	Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen: Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. Asian Test Symposium 2001: 151-156
27	EE	Jun-Weir Lin, Chung-Len Lee, Chau-chin Su, Jwu E. Chen: Fault Diagnosis for Linear Analog Circuits. J. Electronic Testing 17(6): 483-494 (2001)
2000
26	EE	Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30
25	EE	Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen: Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343
24	EE	Chin-Te Kao, Sam Wu, Jwu E. Chen: A case study of failure analysis and guardband determination for a 64M-bit DRAM. Asian Test Symposium 2000: 447-
23	EE	Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su: A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95
22	EE	Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir: Oscillation Ring Delay Test for High Performance Microprocessors. J. Electronic Testing 16(1-2): 147-155 (2000)
21	EE	Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su: A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000)
1999
20	EE	Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen: A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. 15(6): 885-897 (1999)
1998
19	EE	Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen: Maximization of power dissipation under random excitation for burn-in testing. ITC 1998: 567-576
18	EE	Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS 1998: 341-347
17	EE	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14(3): 669-686 (1998)
1997
16	EE	Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen: Fault diagnosis of odd-even sorting networks. Asian Test Symposium 1997: 288-
15	EE	Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Functional test pattern generation for CMOS operational amplifier. VTS 1997: 267-273
14	EE	Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Identifying invalid states for sequential circuit test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1025-1033 (1997)
1996
13	EE	Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15
12	EE	Jwu E. Chen: Yield Improvement by Test Error Cancellation. Asian Test Symposium 1996: 258-262
1995
11	EE	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: Identification of robust untestable path delay faults. Asian Test Symposium 1995: 229-
10	EE	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen: Fanout fault analysis for digital logic circuits. Asian Test Symposium 1995: 33-39
9	EE	Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Factorization of Multi-Valued Logic Functions. ISMVL 1995: 164-169
8	EE	Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Identifying Untestable Faults in Sequential Circuits. IEEE Design & Test of Computers 12(3): 14-23 (1995)
1994
7		Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee: TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC 1994: 508-512
6		Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin: Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC 1994: 661
5		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Complete Test Set for Multiple-Valued Logic Networks. ISMVL 1994: 289-296
4		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL 1994: 44-51
1992
3		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL 1992: 181-188
1991
2	EE	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1559-1568 (1991)
1	EE	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Checkpoints in irredundant two-level combinational circuits. J. Electronic Testing 2(4): 395-397 (1991)

Coauthor Index

1	Magdy S. Abadir	[22]
2	Chi Peng Chang	[31]
3	Soon-Jyh Chang	[15] [29] [32]
4	Yao-Wen Chang	[35] [40] [41] [43]
5	Yeong-Jar Chang	[21]
6	Beyin Chen	[10]
7	Guan-Xun Chen	[33]
8	J.-W. Hsia	[28]
9	Chih Wei Hu	[16]
10	Kuo-Chan Huang	[19] [20]
11	Yin-Chao Huang	[23]
12	R.-L. Jiang	[28]
13	Tagin Jiang	[36]
14	Chin-Te Kao	[24]
15	Chung-Len Lee	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [25] [26] [27] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43]
16	Katherine Shu-Min Li	[34] [35] [36] [39] [40] [41] [42] [43]
17	Hsing-Chung Liang	[8] [13] [14] [18]
18	Jun-Weir Lin	[23] [26] [27] [30]
19	Meng Chiy Lin	[7]
20	Shih Ping Lin	[37] [38]
21	Won Yih Lin	[6]
22	Chih-Wen Lu	[25]
23	Wen-Zen Shen	[1] [2] [10]
24	Chau-chin Su	[27]
25	Chauchin Su	[21] [23] [25] [26] [34] [35] [36] [39] [40] [41] [42] [43]
26	Chih-Hu Wang	[28]
27	Hui Min Wang	[3] [4] [5] [9]
28	Mill-Jer Wang	[28]
29	Ming Shae Wu	[22] [31]
30	Sam Wu	[24]
31	Wen Ching Wu	[6] [11] [16] [17] [22]

Colors in the list of coauthors