2006 |
27 | EE | Haldun Haznedar,
Martin Gall,
Vladimir Zolotov,
Pon Sung Ku,
Chanhee Oh,
Rajendran Panda:
Impact of stress-induced backflow on full-chip electromigration risk assessment.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1038-1046 (2006) |
2005 |
26 | | Murat R. Becer,
Vladimir Zolotov,
Rajendran Panda,
Amir Grinshpon,
Ilan Algor,
Rafi Levy,
Chanhee Oh:
Pessimism reduction in crosstalk noise aware STA.
ICCAD 2005: 954-961 |
25 | EE | Mini Nanua,
David Blaauw,
Chanhee Oh:
Leakage Current Modeling in PD SOI Circuits.
ISQED 2005: 113-117 |
2004 |
24 | EE | Alexey Glebov,
Sergey Gavrilov,
Vladimir Zolotov,
Chanhee Oh,
Rajendran Panda,
Murat R. Becer:
False-Noise Analysis for Domino Circuits.
DATE 2004: 784-789 |
23 | EE | Alexey Glebov,
Sergey Gavrilov,
R. Soloviev,
Vladimir Zolotov,
Murat R. Becer,
Chanhee Oh,
Rajendran Panda:
Delay noise pessimism reduction by logic correlations.
ICCAD 2004: 160-167 |
22 | EE | Chanhee Oh,
Haldun Haznedar,
Martin Gall,
Amir Grinshpon,
Vladimir Zolotov,
Pon Sung Ku,
Rajendran Panda:
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.
ISQED 2004: 232-237 |
21 | EE | Murat R. Becer,
David Blaauw,
Ilan Algor,
Rajendran Panda,
Chanhee Oh,
Vladimir Zolotov,
Ibrahim N. Hajj:
Postroute gate sizing for crosstalk noise reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004) |
20 | EE | Murat R. Becer,
Ravi Vaidyanathan,
Chanhee Oh,
Rajendran Panda:
Crosstalk noise control in an SoC physical design flow.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 488-497 (2004) |
2003 |
19 | EE | Murat R. Becer,
David Blaauw,
Ilan Algor,
Rajendran Panda,
Chanhee Oh,
Vladimir Zolotov,
Ibrahim N. Hajj:
Post-route gate sizing for crosstalk noise reduction.
DAC 2003: 954-957 |
18 | EE | Murat R. Becer,
Ravi Vaidyanathan,
Chanhee Oh,
Rajendran Panda:
Signal integrity management in an SoC physical design flow.
ISPD 2003: 39-46 |
17 | EE | Murat R. Becer,
David Blaauw,
Ilan Algor,
Rajendran Panda,
Chanhee Oh,
Vladimir Zolotov,
Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction.
ISQED 2003: 171-176 |
16 | EE | Chanhee Oh,
David Blaauw,
Murat R. Becer,
Vladimir Zolotov,
Rajendran Panda,
Aurobindo Dasgupta:
Static Electromigration Analysis for Signal Interconnects.
ISQED 2003: 377- |
15 | EE | David Blaauw,
Supamas Sirichotiyakul,
Chanhee Oh:
Driver modeling and alignment for worst-case delay noise.
IEEE Trans. VLSI Syst. 11(2): 157-166 (2003) |
14 | EE | David Blaauw,
Chanhee Oh,
Vladimir Zolotov,
Aurobindo Dasgupta:
Static electromigration analysis for on-chip signal interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003) |
2002 |
13 | EE | Vladimir Zolotov,
David Blaauw,
Supamas Sirichotiyakul,
Murat R. Becer,
Chanhee Oh,
Rajendran Panda,
Amir Grinshpon,
Rafi Levy:
Noise propagation and failure criteria for VLSI designs.
ICCAD 2002: 587-594 |
12 | EE | Vladimir Zolotov,
David Blaauw,
Rajendran Panda,
Chanhee Oh:
Noise Injection and Propagation in High Performance Designs.
ISQED 2002: 425-430 |
11 | EE | Alexey Glebov,
Sergey Gavrilov,
David Blaauw,
Vladimir Zolotov,
Rajendran Panda,
Chanhee Oh:
False-Noise Analysis Using Resolution Method.
ISQED 2002: 437- |
10 | EE | Supamas Sirichotiyakul,
Tim Edwards,
Chanhee Oh,
Rajendran Panda,
David Blaauw:
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits.
IEEE Trans. VLSI Syst. 10(2): 79-90 (2002) |
2001 |
9 | EE | Supamas Sirichotiyakul,
David Blaauw,
Chanhee Oh,
Rafi Levy,
Vladimir Zolotov,
Jingyan Zuo:
Driver Modeling and Alignment for Worst-Case Delay Noise.
DAC 2001: 720-725 |
8 | EE | Alexey Glebov,
Sergey Gavrilov,
David Blaauw,
Supamas Sirichotiyakul,
Chanhee Oh,
Vladimir Zolotov:
False-Noise Analysis using Logic Implications.
ICCAD 2001: 515- |
7 | EE | Murat R. Becer,
David Blaauw,
Supamas Sirichotiyakul,
Chanhee Oh,
Vladimir Zolotov,
Jingyan Zuo,
Rafi Levy,
Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
ISQED 2001: 158- |
2000 |
6 | EE | Rafi Levy,
David Blaauw,
Gabi Braca,
Aurobindo Dasgupta,
Amir Grinshpon,
Chanhee Oh,
Boaz Orshav,
Supamas Sirichotiyakul,
Vladimir Zolotov:
ClariNet: a noise analysis tool for deep submicron design.
DAC 2000: 233-238 |
5 | | David Blaauw,
Vladimir Zolotov,
Savithri Sundareswaran,
Chanhee Oh,
Rajendran Panda:
Slope Propagation in Static Timing Analysis.
ICCAD 2000: 338-343 |
1999 |
4 | EE | Supamas Sirichotiyakul,
Tim Edwards,
Chanhee Oh,
Jingyan Zuo,
Abhijit Dharchoudhury,
Rajendran Panda,
David Blaauw:
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.
DAC 1999: 436-441 |
1998 |
3 | EE | David Blaauw,
Abhijit Dharchoudhury,
Rajendran Panda,
Supamas Sirichotiyakul,
Chanhee Oh,
Tim Edwards:
Emerging power management tools for processor design.
ISLPED 1998: 143-148 |
1996 |
2 | EE | Chanhee Oh,
M. Ray Mercer:
Efficient logic-level timing analysis using constraint-guided critical path search.
IEEE Trans. VLSI Syst. 4(3): 346-355 (1996) |
1994 |
1 | | Ronn B. Brashear,
Noel Menezes,
Chanhee Oh,
Lawrence T. Pillage,
M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.
EDAC-ETC-EUROASIC 1994: 332-337 |