| 2009 |
|---|
| 244 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis.
FPGA 2009: 151-160 |
| 243 | EE | Stephen Jang,
Dennis Wu,
Mark Jarvin,
Billy Chan,
Kevin Chung,
Alan Mishchenko,
Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis.
FPGA 2009: 237-240 |
| 2008 |
|---|
| 242 | EE | Aaron P. Hurst,
Alan Mishchenko,
Robert K. Brayton:
Scalable min-register retiming under timing and initializability constraints.
DAC 2008: 534-539 |
| 241 | EE | Michael L. Case,
Victor N. Kravets,
Alan Mishchenko,
Robert K. Brayton:
Merging nodes under sequential observability.
DAC 2008: 540-545 |
| 240 | EE | Alan Mishchenko,
Michael L. Case,
Robert K. Brayton,
Stephen Jang:
Scalable and scalably-verifiable sequential synthesis.
ICCAD 2008: 234-241 |
| 239 | EE | Alan Mishchenko,
Robert K. Brayton,
Satrajit Chatterjee:
Boolean factoring and decomposition of logic networks.
ICCAD 2008: 38-44 |
| 238 | EE | Fan Mo,
Robert K. Brayton:
Placement based multiplier rewiring for cell-based designs.
ICCAD 2008: 430-433 |
| 237 | EE | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Compositionally Progressive Solutions of Synchronous FSM Equations.
Discrete Event Dynamic Systems 18(1): 51-89 (2008) |
| 2007 |
|---|
| 236 | EE | Tiziano Villa,
Svetlana Zharikova,
Nina Yevtushenko,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A new algorithm for the largest compositionally progressive solution of synchronous language equations.
ACM Great Lakes Symposium on VLSI 2007: 441-444 |
| 235 | EE | Yu-Shen Yang,
Subarnarekha Sinha,
Andreas G. Veneris,
Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs.
ASP-DAC 2007: 402-407 |
| 234 | EE | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton,
Andreas Kuehlmann:
On Resolution Proofs for Combinational Equivalence.
DAC 2007: 600-605 |
| 233 | EE | Michael L. Case,
Alan Mishchenko,
Robert K. Brayton:
Automated Extraction of Inductive Invariants to Aid Model Checking.
FMCAD 2007: 165-172 |
| 232 | EE | Aaron P. Hurst,
Alan Mishchenko,
Robert K. Brayton:
Fast Minimum-Register Retiming via Binary Maximum-Flow.
FMCAD 2007: 181-187 |
| 231 | EE | Alan Mishchenko,
Sungmin Cho,
Satrajit Chatterjee,
Robert K. Brayton:
Combinational and sequential mapping with priority cuts.
ICCAD 2007: 354-361 |
| 230 | EE | Fan Mo,
Robert K. Brayton:
A simultaneous bus orientation and bused pin flipping algorithm.
ICCAD 2007: 386-389 |
| 229 | EE | Fan Mo,
Robert K. Brayton:
Semi-detailed bus routing with variation reduction.
ISPD 2007: 143-150 |
| 228 | EE | Alan Mishchenko,
Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization
CoRR abs/0710.4695: (2007) |
| 227 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Tiziano Villa,
Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations
CoRR abs/0710.4743: (2007) |
| 226 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton:
Improvements to Technology Mapping for LUT-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 240-253 (2007) |
| 2006 |
|---|
| 225 | EE | Jin S. Zhang,
Alan Mishchenko,
Robert K. Brayton,
Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.
DAC 2006: 510-515 |
| 224 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton:
DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
DAC 2006: 532-535 |
| 223 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton:
Improvements to technology mapping for LUT-based FPGAs.
FPGA 2006: 41-49 |
| 222 | EE | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton:
Factor cuts.
ICCAD 2006: 143-150 |
| 221 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton,
Niklas Eén:
Improvements to combinational equivalence checking.
ICCAD 2006: 836-843 |
| 220 | EE | Jie-Hong Roland Jiang,
Robert K. Brayton:
Retiming and Resynthesis: A Complexity Perspective.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2674-2686 (2006) |
| 219 | EE | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton,
Xinning Wang,
Timothy Kam:
Reducing Structural Bias in Technology Mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2894-2903 (2006) |
| 218 | EE | Alan Mishchenko,
Jin S. Zhang,
Subarnarekha Sinha,
Jerry R. Burch,
Robert K. Brayton,
Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 743-755 (2006) |
| 217 | EE | Alan Mishchenko,
Robert K. Brayton:
A theory of nondeterministic networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 977-999 (2006) |
| 2005 |
|---|
| 216 | EE | Yinghua Li,
Alex Kondratyev,
Robert K. Brayton:
Gaining Predictability and Noise Immunity in Global Interconnects.
ACSD 2005: 176-185 |
| 215 | EE | Alan Mishchenko,
Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization.
DATE 2005: 412-417 |
| 214 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Tiziano Villa,
Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations.
DATE 2005: 418-423 |
| 213 | | Yinghua Li,
Alex Kondratyev,
Robert K. Brayton:
Synthesis methodology for built-in at-speed testing.
ICCAD 2005: 183-188 |
| 212 | | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton,
Xinning Wang,
Timothy Kam:
Reducing structural bias in technology mapping.
ICCAD 2005: 519-526 |
| 2004 |
|---|
| 211 | EE | Jie-Hong Roland Jiang,
Robert K. Brayton:
Functional Dependency for Verification Reduction.
CAV 2004: 268-280 |
| 210 | EE | Fan Mo,
Robert K. Brayton:
A timing-driven module-based chip design flow.
DAC 2004: 67-70 |
| 209 | EE | Jie-Hong Roland Jiang,
Alan Mishchenko,
Robert K. Brayton:
On breakable cyclic definitions.
ICCAD 2004: 411-418 |
| 208 | EE | Satrajit Chatterjee,
Robert K. Brayton:
A new incremental placement algorithm and its application to congestion-aware divisor extraction.
ICCAD 2004: 541-548 |
| 207 | EE | Sunil P. Khatri,
Subarnarekha Sinha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
SPFD-based wire removal in standard-cell and network-of-PLA circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004) |
| 2003 |
|---|
| 206 | EE | Yunjian Jiang,
Slobodan Matic,
Robert K. Brayton:
Generalized cofactoring for logic function evaluation.
DAC 2003: 155-158 |
| 205 | EE | Jie-Hong Roland Jiang,
Alan Mishchenko,
Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary.
DATE 2003: 10752-10757 |
| 204 | EE | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
DATE 2003: 11154-11155 |
| 203 | EE | Alan Mishchenko,
Robert K. Brayton:
A Theory of Non-Deterministic Networks.
ICCAD 2003: 709-717 |
| 202 | EE | Fan Mo,
Robert K. Brayton:
Fishbone: a block-level placement and routing scheme.
ISPD 2003: 204-209 |
| 201 | EE | Vigyan Singhal,
Carl Pixley,
Adnan Aziz,
Shaz Qadeer,
Robert K. Brayton:
Sequential optimization in the absence of global reset.
ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) |
| 200 | EE | Jie-Hong Roland Jiang,
Robert K. Brayton:
On the verification of sequential equivalence.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 686-697 (2003) |
| 199 | EE | Fan Mo,
Robert K. Brayton:
PLA-based regular structures and their synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 723-729 (2003) |
| 2002 |
|---|
| 198 | EE | Massimo Baleani,
Frank Gennari,
Yunjian Jiang,
Yatish Patel,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform.
CODES 2002: 151-156 |
| 197 | EE | Fan Mo,
Robert K. Brayton:
River PLAs: a regular circuit structure.
DAC 2002: 201-206 |
| 196 | EE | Yunjian Jiang,
Robert K. Brayton:
Software synthesis from synchronous specifications using logic simulation techniques.
DAC 2002: 319-324 |
| 195 | EE | Evguenii I. Goldberg,
Mukul R. Prasad,
Robert K. Brayton:
Using Problem Symmetry in Search Based Satisfiability Algorithms.
DATE 2002: 134-141 |
| 194 | EE | Fan Mo,
Robert K. Brayton:
Whirlpool PLAs: a regular logic structure and their synthesis.
ICCAD 2002: 543-550 |
| 193 | EE | Alan Mishchenko,
Robert K. Brayton:
Simplification of non-deterministic multi-valued networks.
ICCAD 2002: 557-562 |
| 192 | EE | Subarnarekha Sinha,
Alan Mishchenko,
Robert K. Brayton:
Topologically constrained logic synthesis.
ICCAD 2002: 679-686 |
| 191 | EE | Robert K. Brayton,
M. Gao,
Jie-Hong Roland Jiang,
Yunjian Jiang,
Yinghua Li,
Alan Mishchenko,
Subarnarekha Sinha,
Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks.
ISMVL 2002: 168- |
| 190 | | Subarnarekha Sinha,
Alan Mishchenko,
Robert K. Brayton:
Topologically Constrained Logic Synthesis.
IWLS 2002: 13-20 |
| 189 | | Alan Mishchenko,
Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis.
IWLS 2002: 173-177 |
| 188 | | Jie-Hong Roland Jiang,
Robert K. Brayton:
On the Verification of Sequential Equivalence.
IWLS 2002: 307-314 |
| 187 | | Yunjian Jiang,
Robert K. Brayton:
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic.
IWLS 2002: 327-332 |
| 186 | | Alan Mishchenko,
Robert K. Brayton:
Simplification of Non-Deterministic Multi-Valued Networks.
IWLS 2002: 333-338 |
| 185 | | Jie-Hong Roland Jiang,
Alan Mishchenko,
Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary.
IWLS 2002: 339-344 |
| 184 | | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
IWLS 2002: 45-50 |
| 183 | | Fan Mo,
Robert K. Brayton:
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design.
IWLS 2002: 7-12 |
| 182 | | Adnan Aziz,
Thomas R. Shiple,
Vigyan Singhal,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Formula-Dependent Equivalence for Compositional CTL Model Checking.
Formal Methods in System Design 21(2): 193-224 (2002) |
| 2001 |
|---|
| 181 | EE | Yunjian Jiang,
Robert K. Brayton:
Logic optimization and code generation for embedded control applications.
CODES 2001: 225-229 |
| 180 | EE | Evguenii I. Goldberg,
Mukul R. Prasad,
Robert K. Brayton:
Using SAT for combinational equivalence checking.
DATE 2001: 114-121 |
| 179 | EE | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Solution of Parallel Language Equations for Logic Synthesis.
ICCAD 2001: 103- |
| 178 | EE | Fan Mo,
Abdallah Tabbara,
Robert K. Brayton:
A Force-Directed Maze Router.
ICCAD 2001: 404-407 |
| 177 | EE | Robert K. Brayton:
Compatible Observability Don't Cares Revisited.
ICCAD 2001: 618- |
| 176 | EE | Subarnarekha Sinha,
Andreas Kuehlmann,
Robert K. Brayton:
Sequential SPFDs.
ICCAD 2001: 84-90 |
| 175 | | Fan Mo,
Abdallah Tabbara,
Robert K. Brayton:
A Timing-Driven Macro-Cell Placement Algorithm.
ICCD 2001: 322-327 |
| 174 | | Rajeev Alur,
Robert K. Brayton,
Thomas A. Henzinger,
Shaz Qadeer,
Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State-Space Exploration.
Formal Methods in System Design 18(2): 97-116 (2001) |
| 173 | EE | Vigyan Singhal,
Carl Pixley,
Adnan Aziz,
Robert K. Brayton:
Theory of safe replacements for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 249-265 (2001) |
| 2000 |
|---|
| 172 | EE | Dirk-Jan Jongeneel,
Yosinori Watanabe,
Robert K. Brayton,
Ralph H. J. M. Otten:
Area and search space control for technology mapping.
DAC 2000: 86-91 |
| 171 | | Fan Mo,
Abdallah Tabbara,
Robert K. Brayton:
A Force-Directed Macro-Cell Placer.
ICCAD 2000: 177-180 |
| 170 | | Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric.
ICCAD 2000: 412-418 |
| 169 | | Yunjian Jiang,
Robert K. Brayton:
Don't Cares and Multi-Valued Logic Network Minimization.
ICCAD 2000: 520-525 |
| 168 | EE | Subarnarekha Sinha,
Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.
ICCD 2000: 494-503 |
| 167 | EE | Adnan Aziz,
Kumud Sanwal,
Vigyan Singhal,
Robert K. Brayton:
Model-checking continous-time Markov chains.
ACM Trans. Comput. Log. 1(1): 162-170 (2000) |
| 166 | | Stefano Quer,
Gianpiero Cabodi,
Paolo Camurati,
Luciano Lavagno,
Ellen Sentovich,
Robert K. Brayton:
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.
Formal Methods in System Design 17(2): 107-134 (2000) |
| 165 | EE | Adnan Aziz,
Felice Balarin,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1149-1162 (2000) |
| 164 | EE | Evguenii I. Goldberg,
Luca P. Carloni,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Negative thinking in branch-and-bound: the case of unate covering.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 281-294 (2000) |
| 163 | EE | Ralph H. J. M. Otten,
Robert K. Brayton:
Performance planning.
Integration 29(1): 1-24 (2000) |
| 162 | EE | Abdallah Tabbara,
Bassam Tabbara,
Robert K. Brayton,
A. Richard Newton:
Integration of retiming with architectural floorplanning.
Integration 29(1): 25-43 (2000) |
| 1999 |
|---|
| 161 | EE | Sunil P. Khatri,
Amit Mehrotra,
Robert K. Brayton,
Ralph H. J. M. Otten,
Alberto L. Sangiovanni-Vincentelli:
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications.
DAC 1999: 491-496 |
| 160 | EE | Abdallah Tabbara,
Robert K. Brayton,
A. Richard Newton:
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints.
DAC 1999: 725-730 |
| 159 | EE | Rajeev K. Ranjan,
Vigyan Singhal,
Fabio Somenzi,
Robert K. Brayton:
Using Combinational Verification for Sequential Circuits.
DATE 1999: 138-144 |
| 158 | EE | Yuji Kukimoto,
Robert K. Brayton:
Timing-safe false path removal for combinational modules.
ICCAD 1999: 544-550 |
| 157 | EE | Andreas Kuehlmann,
Kenneth L. McMillan,
Robert K. Brayton:
Probabilistic state space search.
ICCAD 1999: 574-579 |
| 156 | | Luca P. Carloni,
Evguenii I. Goldberg,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.
VLSI 1999: 346-361 |
| 155 | | Robert K. Brayton,
Sunil P. Khatri:
Multi-Valued Logic Synthesis.
VLSI Design 1999: 196-105 |
| 154 | EE | Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential Multi-Valued Network Simplification using Redundancy Removal.
VLSI Design 1999: 206-211 |
| 1998 |
|---|
| 153 | EE | Zhongcheng Li,
Yinghua Min,
Robert K. Brayton:
A New Low-Cost Method for Identifying Untestable Path Delay Faults.
Asian Test Symposium 1998: 76-81 |
| 152 | | Gurmeet Singh Manku,
Ramin Hojati,
Robert K. Brayton:
Structural Symmetry and Model Checking.
CAV 1998: 159-171 |
| 151 | | Adrian J. Isles,
Ramin Hojati,
Robert K. Brayton:
Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory.
CAV 1998: 256-267 |
| 150 | EE | Ralph H. J. M. Otten,
Robert K. Brayton:
Planning for Performance.
DAC 1998: 122-127 |
| 149 | EE | Yuji Kukimoto,
Robert K. Brayton,
Prashant Sawkar:
Delay-Optimal Technology Mapping by DAG Covering.
DAC 1998: 348-351 |
| 148 | EE | Yuji Kukimoto,
Robert K. Brayton:
Hierarchical Functional Timing Analysis.
DAC 1998: 580-585 |
| 147 | EE | Evguenii I. Goldberg,
Yuji Kukimoto,
Robert K. Brayton:
Combinational Verification based on High-Level Functional Specifications.
DATE 1998: 803- |
| 146 | EE | Subarnarekha Sinha,
Robert K. Brayton:
Implementation and use of SPFDs in optimizing Boolean networks.
ICCAD 1998: 103-110 |
| 145 | EE | Wilsin Gosti,
Amit Narayan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Wireplanning in logic synthesis.
ICCAD 1998: 26-33 |
| 144 | EE | Rajeev K. Ranjan,
Vigyan Singhal,
Fabio Somenzi,
Robert K. Brayton:
On the optimization power of retiming and resynthesis transformations.
ICCAD 1998: 402-407 |
| 143 | EE | Gitanjali Swamy,
Stephen A. Edwards,
Robert K. Brayton:
Efficient Verification and Synthesis using Design Commonalities.
VLSI Design 1998: 542-551 |
| 142 | EE | Evguenii I. Goldberg,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Theory and algorithms for face hypercube embedding.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 472-488 (1998) |
| 1997 |
|---|
| 141 | | Serdar Tasiran,
Robert K. Brayton:
STARI: A Case Study in Compositional and Hierarchical Timing Verification.
CAV 1997: 191-201 |
| 140 | | Rajeev Alur,
Robert K. Brayton,
Thomas A. Henzinger,
Shaz Qadeer,
Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State Space Exploration.
CAV 1997: 340-351 |
| 139 | EE | Yuji Kukimoto,
Robert K. Brayton:
Exact Required Time Analysis via False Path Detection.
DAC 1997: 220-225 |
| 138 | EE | Yuji Kukimoto,
Wilsin Gosti,
Alexander Saldanha,
Robert K. Brayton:
Approximate timing analysis of combinational circuits under the XBD0 model.
ICCAD 1997: 176-181 |
| 137 | EE | Amit Mehrotra,
Shaz Qadeer,
Vigyan Singhal,
Robert K. Brayton,
Adnan Aziz,
Alberto L. Sangiovanni-Vincentelli:
Sequential optimisation without state space exploration.
ICCAD 1997: 208-215 |
| 136 | EE | Evguenii I. Goldberg,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A fast and robust exact algorithm for face embedding.
ICCAD 1997: 296-303 |
| 135 | EE | Amit Narayan,
Adrian J. Isles,
Jawahar Jain,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Reachability analysis using partitioned-ROBDDs.
ICCAD 1997: 388-393 |
| 134 | EE | Evguenii I. Goldberg,
Luca P. Carloni,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Negative thinking by incremental problem solving: application to unate covering.
ICCAD 1997: 91-98 |
| 133 | | Rajeev K. Ranjan,
Wilsin Gosti,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions.
ICCD 1997: 344-351 |
| 132 | | Zhongcheng Li,
Yuhong Zhao,
Yinghua Min,
Robert K. Brayton:
Timed Binary Decision Diagrams.
ICCD 1997: 352-357 |
| 131 | | Zhongcheng Li,
Robert K. Brayton,
Yinghua Min:
Efficient Identification of Non-Robustly Untestable Path Delay Faults.
ITC 1997: 992-997 |
| 130 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Theory and algorithms for state minimization of nondeterministic FSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1311-1322 (1997) |
| 129 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Implicit computation of compatible sets for state minimization of ISFSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 657-676 (1997) |
| 128 | EE | Tiziano Villa,
Timothy Kam,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Explicit and implicit algorithms for binate covering problems.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 677-691 (1997) |
| 127 | EE | Tiziano Villa,
Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Symbolic two-level minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 692-708 (1997) |
| 1996 |
|---|
| 126 | | Adnan Aziz,
Kumud Sanwal,
Vigyan Singhal,
Robert K. Brayton:
Verifying Continuous Time Markov Chains.
CAV 1996: 269-276 |
| 125 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS: A System for Verification and Synthesis.
CAV 1996: 428-432 |
| 124 | | Serdar Tasiran,
Rajeev Alur,
Robert P. Kurshan,
Robert K. Brayton:
Verifying Abstractions of Timed Systems.
CONCUR 1996: 546-562 |
| 123 | EE | Sunil P. Khatri,
Amit Narayan,
Sriram C. Krishnan,
Kenneth L. McMillan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Engineering Change in a Non-Deterministic FSM Setting.
DAC 1996: 451-456 |
| 122 | EE | Jagesh V. Sanghavi,
Rajeev K. Ranjan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
High Performance BDD Package By Exploiting Memory Hiercharchy.
DAC 1996: 635-640 |
| 121 | | Ramin Hojati,
Adrian J. Isles,
Desmond Kirkpatrick,
Robert K. Brayton:
Verification Using Uninterpreted Functions and Finite Instantiations.
FMCAD 1996: 218-232 |
| 120 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS.
FMCAD 1996: 248-256 |
| 119 | | Jawahar Jain,
Amit Narayan,
C. Coelho,
Sunil P. Khatri,
Alberto L. Sangiovanni-Vincentelli,
Robert K. Brayton,
Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction.
FMCAD 1996: 419-434 |
| 118 | EE | Vigyan Singhal,
Sharad Malik,
Robert K. Brayton:
The case for retiming with explicit reset circuitry.
ICCAD 1996: 618-625 |
| 117 | EE | Ramin Hojati,
Sriram C. Krishnan,
Robert K. Brayton:
Early Quantification and Partitioned Transition Relations.
ICCD 1996: 12-19 |
| 116 | EE | Rajeev K. Ranjan,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Binary decision diagrams on network of workstation.
ICCD 1996: 358-364 |
| 115 | EE | Shaz Qadeer,
Robert K. Brayton,
Vigyan Singhal:
Latch Redundancy Removal Without Global Reset.
ICCD 1996: 432-439 |
| 114 | EE | Amit Narayan,
Sunil P. Khatri,
Jawahar Jain,
Masahiro Fujita,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs.
VLSI Design 1996: 249-253 |
| 113 | EE | Yosinori Watanabe,
Lisa M. Guerra,
Robert K. Brayton:
Permissible functions for multioutput components in combinational logic optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 732-744 (1996) |
| 112 | EE | William K. C. Lam,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Valid clock frequencies and their computation in wavepipelined circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 791-807 (1996) |
| 111 | EE | Paul R. Stephan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Combinational test generation using satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1167-1176 (1996) |
| 1995 |
|---|
| 110 | | Sriram C. Krishnan,
Anuj Puri,
Robert K. Brayton,
Pravin Varaiya:
The Rabin Index and Chain Automata, with Applications to Automatas and Games.
CAV 1995: 253-266 |
| 109 | | Adnan Aziz,
Felice Balarin,
Robert K. Brayton,
M. D. DiBenedetto,
Alexander Saldanha:
Supervisory Control of Finite State Machines.
CAV 1995: 279-292 |
| 108 | | Ramin Hojati,
Robert K. Brayton:
Automatic Datapath Abstraction In Hardware Systems.
CAV 1995: 98-113 |
| 107 | | Serdar Tasiran,
Ramin Hojati,
Robert K. Brayton:
Language containment of non-deterministic omega-automata.
CHARME 1995: 261-277 |
| 106 | EE | Vigyan Singhal,
Carl Pixley,
Richard L. Rudell,
Robert K. Brayton:
The Validity of Retiming Sequential Circuits.
DAC 1995: 316-321 |
| 105 | EE | Vigyan Singhal,
Carl Pixley,
Adnan Aziz,
Robert K. Brayton:
Exploiting power-up delay for sequential optimization.
EURO-DAC 1995: 54-59 |
| 104 | EE | Adnan Aziz,
Felice Balarin,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S.
ICCAD 1995: 612-617 |
| 103 | EE | Huey-Yih Wang,
Robert K. Brayton:
Multi-level logic optimization of FSM networks.
ICCAD 1995: 728-735 |
| 102 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Implicit state minimization of non-deterministic FSMs.
ICCD 1995: 250-257 |
| 101 | EE | Gitanjali Swamy,
Robert K. Brayton,
Vigyan Singhal:
Incremental methods for FSM traversal.
ICCD 1995: 590- |
| 100 | | Vigyan Singhal,
Robert K. Brayton,
Carl Pixley:
Power-Up Delay for Retiming Digital Circuits.
ISCAS 1995: 566-569 |
| 99 | | Sriram C. Krishnan,
Anuj Puri,
Robert K. Brayton:
Structural Complexity of Omega-Automata.
STACS 1995: 143-156 |
| 98 | EE | Alexander Saldanha,
Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Functional clock schedule optimization.
VLSI Design 1995: 93-98 |
| 97 | | Ramin Hojati,
Robert K. Brayton:
An Environment for Formal Verification Based on Symbolic Computations.
Formal Methods in System Design 6(2): 191-216 (1995) |
| 96 | EE | William K. C. Lam,
Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Delay fault coverage, test set size, and performance trade-offs.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 32-44 (1995) |
| 95 | EE | Luciano Lavagno,
Cho W. Moon,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
An efficient heuristic procedure for solving the state assignment problem for event-based specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 45-60 (1995) |
| 94 | | Hervé J. Touati,
Robert K. Brayton,
Robert P. Kurshan:
Testing Language Containment for omega-Automata Using BDD's
Inf. Comput. 118(1): 101-109 (1995) |
| 1994 |
|---|
| 93 | | William K. C. Lam,
Robert K. Brayton:
Criteria for the Simple Path Property in Timed Automata.
CAV 1994: 27-40 |
| 92 | | Ramin Hojati,
Robert B. Mueller-Thuns,
Robert K. Brayton:
Improving Language Containment Using Fairness Graphs.
CAV 1994: 391-403 |
| 91 | EE | William K. C. Lam,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Exact Minimum Cycle Times for Finite State Machines.
DAC 1994: 100-105 |
| 90 | EE | Thomas R. Shiple,
Ramin Hojati,
Alberto L. Sangiovanni-Vincentelli,
Robert K. Brayton:
Heuristic Minimization of BDDs Using Don't Cares.
DAC 1994: 225-231 |
| 89 | EE | Adnan Aziz,
Serdar Tasiran,
Robert K. Brayton:
BDD Variable Ordering for Interacting Finite State Machines.
DAC 1994: 283-288 |
| 88 | EE | Rajeev Murgai,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Optimum Functional Decomposition Using Encoding.
DAC 1994: 408-414 |
| 87 | EE | Alexander Saldanha,
Heather Harkness,
Patrick C. McGeer,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Performance Optimization Using Exact Sensitization.
DAC 1994: 425-429 |
| 86 | EE | Adnan Aziz,
Felice Balarin,
Szu-Tsung Cheng,
Ramin Hojati,
Timothy Kam,
Sriram C. Krishnan,
Rajeev K. Ranjan,
Thomas R. Shiple,
Vigyan Singhal,
Serdar Tasiran,
Huey-Yih Wang,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
HSIS: A BDD-Based Environment for Formal Verification.
DAC 1994: 454-459 |
| 85 | EE | Huey-Yih Wang,
Robert K. Brayton:
Permissible Observability Relations in FSM Networks.
DAC 1994: 677-683 |
| 84 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A Fully Implicit Algorithm for Exact State Minimization.
DAC 1994: 684-690 |
| 83 | | Yosinori Watanabe,
Robert K. Brayton:
State Minimization of Pseudo Non-Deterministic FSM's.
EDAC-ETC-EUROASIC 1994: 184-191 |
| 82 | | Adnan Aziz,
Vigyan Singhal,
Felice Balarin,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures.
ICALP 1994: 364-375 |
| 81 | EE | Carl Pixley,
Vigyan Singhal,
Adnan Aziz,
Robert K. Brayton:
Multi-level synthesis for safe replaceability.
ICCAD 1994: 442-449 |
| 80 | EE | Gitanjali Swamy,
Robert K. Brayton:
Incremental formal design verification.
ICCAD 1994: 458-465 |
| 79 | EE | Yuji Kukimoto,
Masahiro Fujita,
Robert K. Brayton:
A redesign technique for combinational circuits based on gate reconnections.
ICCAD 1994: 632-637 |
| 78 | | Ellen Sentovich,
Robert K. Brayton:
An Exact Optimization of Two-Level Acyclic Sequential Circuits.
ICCD 1994: 242-249 |
| 77 | | Adnan Aziz,
Vigyan Singhal,
Gitanjali Swamy,
Robert K. Brayton:
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment.
ICCD 1994: 255-261 |
| 76 | | Sriram C. Krishnan,
Anuj Puri,
Robert K. Brayton:
Deterministic w Automata vis-a-vis Deterministic Buchi Automata.
ISAAC 1994: 378-386 |
| 75 | EE | Alexander Saldanha,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Satisfaction of input and output encoding constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 589-602 (1994) |
| 74 | EE | Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Circuit structure relations to redundancy and delay.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 875-883 (1994) |
| 73 | EE | Cho W. Moon,
Paul R. Stephan,
Robert K. Brayton:
Specification, synthesis, and verification of hazard-free asynchronous circuits.
VLSI Signal Processing 7(1-2): 85-100 (1994) |
| 1993 |
|---|
| 72 | | Robert K. Brayton:
Logic Synthesis and Design Verification.
CAV 1993: 1-2 |
| 71 | | William K. C. Lam,
Robert K. Brayton:
Alternating RQ Timed Automata.
CAV 1993: 237-252 |
| 70 | | Ramin Hojati,
Robert K. Brayton,
Robert P. Kurshan:
BDD-Based Debugging Of Design Using Language Containment and Fair CTL.
CAV 1993: 41-58 |
| 69 | EE | William K. C. Lam,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions.
DAC 1993: 128-134 |
| 68 | EE | Rajeev Murgai,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential Synthesis for Table Look Up Programmable Gate Arrays.
DAC 1993: 224-229 |
| 67 | EE | Yusuke Matsunaga,
Patrick C. McGeer,
Robert K. Brayton:
On Computing the Transitive Closure of a State Transition Relation.
DAC 1993: 260-265 |
| 66 | EE | William K. C. Lam,
Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Delay Fault Coverage and Performance Tradeoffs.
DAC 1993: 446-452 |
| 65 | EE | Ramin Hojati,
Thomas R. Shiple,
Robert K. Brayton,
Robert P. Kurshan:
A Unified Approach to Language Containment and Fair CTL Model Checking.
DAC 1993: 475-481 |
| 64 | EE | Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Resynthesis of Multi-Phase Pipelines.
DAC 1993: 490-496 |
| 63 | EE | Patrick C. McGeer,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Espresso-Signature: A New Exact Minimizer for Logic Functions.
DAC 1993: 618-624 |
| 62 | EE | Cho W. Moon,
Robert K. Brayton:
Elimination of Dynamic hazards by Factoring.
DAC 1993: 7-13 |
| 61 | EE | Rajeev Murgai,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Cube-packing and two-level minimization.
ICCAD 1993: 115-122 |
| 60 | EE | Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Minimum padding to satisfy short path constraints.
ICCAD 1993: 156-161 |
| 59 | EE | Yosinori Watanabe,
Robert K. Brayton:
The maximum set of permissible behaviors for FSM networks.
ICCAD 1993: 316-320 |
| 58 | EE | Huey-Yih Wang,
Robert K. Brayton:
Input don't care sequences in FSM networks.
ICCAD 1993: 321-328 |
| 57 | | Yosinori Watanabe,
Lisa M. Guerra,
Robert K. Brayton:
Logic Optimization with Multi-Output Gates.
ICCD 1993: 416-420 |
| 56 | | Vigyan Singhal,
Yosinori Watanabe,
Robert K. Brayton:
Heuristic Minimization of Synchronous Relations.
ICCD 1993: 428-433 |
| 55 | | Paul R. Stephan,
Robert K. Brayton:
Physically Realizable Gate Models.
ICCD 1993: 442-445 |
| 54 | | Rajeev Murgai,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.
ICCD 1993: 505-512 |
| 53 | | Patrick C. McGeer,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Minimization of Logic Functions Using Essential Signature Sets.
VLSI Design 1993: 323-328 |
| 52 | | Abdul A. Malik,
Robert K. Brayton,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Two-Level Minimization of Multivalued Functions with Large Offsets.
IEEE Trans. Computers 42(11): 1325-1342 (1993) |
| 51 | EE | Patrick C. McGeer,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
ESPRESSO-SIGNATURE: a new exact minimizer for logic functions.
IEEE Trans. VLSI Syst. 1(4): 432-440 (1993) |
| 50 | EE | Hervé J. Touati,
Robert K. Brayton:
Computing the initial states of retimed circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 157-162 (1993) |
| 49 | EE | Yosinori Watanabe,
Robert K. Brayton:
Heuristic minimization of multiple-valued relations.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1458-1472 (1993) |
| 48 | EE | Sharad Malik,
Kanwar Jit Singh,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 568-578 (1993) |
| 1992 |
|---|
| 47 | | Thomas R. Shiple,
Massimiliano Chiodo,
Alberto L. Sangiovanni-Vincentelli,
Robert K. Brayton:
Automatic Reduction in CTL Compositional Model Checking.
CAV 1992: 234-247 |
| 46 | | Ramin Hojati,
Hervé J. Touati,
Robert P. Kurshan,
Robert K. Brayton:
Efficient omega-Regular Language Containment.
CAV 1992: 396-409 |
| 45 | EE | Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation.
DAC 1992: 173-176 |
| 44 | EE | Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited.
DAC 1992: 245-248 |
| 43 | EE | Rajeev Murgai,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
An Improved Synthesis Algorithm for Multiplexor-Based PGA's.
DAC 1992: 380-386 |
| 42 | EE | Narendra V. Shenoy,
Kanwar Jit Singh,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
On the Temporal Equivalence of Sequential Circuits.
DAC 1992: 405-409 |
| 41 | EE | Luciano Lavagno,
Cho W. Moon,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Solving the State Assignment Problem for Signal Transition Graphs.
DAC 1992: 568-572 |
| 40 | EE | Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Graph algorithms for clock schedule optimization.
ICCAD 1992: 132-136 |
| 39 | EE | Massimiliano Chiodo,
Thomas R. Shiple,
Alberto L. Sangiovanni-Vincentelli,
Robert K. Brayton:
Automatic compositional minimization in CTL model checking.
ICCAD 1992: 172-178 |
| 38 | EE | William K. C. Lam,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Valid clocking in wavepipelined circuits.
ICCAD 1992: 518-525 |
| 37 | | Ellen Sentovich,
Kanwar Jit Singh,
Cho W. Moon,
Hamid Savoj,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential Circuit Design Using Synthesis and Optimization.
ICCD 1992: 328-333 |
| 36 | | William K. C. Lam,
Robert K. Brayton:
On Relationship Between ITE and BDD.
ICCD 1992: 448-451 |
| 35 | | Paul T. Gutwin,
Patrick C. McGeer,
Robert K. Brayton:
Delay Prediction for Technology-Independent Logic Equations.
ICCD 1992: 468-471 |
| 34 | EE | Sharad Malik,
Luciano Lavagno,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Symbolic minimization of multilevel logic and the input encoding problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 825-843 (1992) |
| 1991 |
|---|
| 33 | EE | Alexander Saldanha,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A Framework for Satisfying Input and Output Encoding Constraints.
DAC 1991: 170-175 |
| 32 | | Yosinori Watanabe,
Robert K. Brayton:
Heuristic Minimazation of Multiple-Valued Relations.
ICCAD 1991: 126-129 |
| 31 | | Patrick C. McGeer,
Alexander Saldanha,
Paul R. Stephan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.
ICCAD 1991: 180-183 |
| 30 | | Patrick C. McGeer,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli,
Sartaj Sahni:
Performance Enhancement through the Generalized Bypass Transform.
ICCAD 1991: 184-187 |
| 29 | | Hervé J. Touati,
Hamid Savoj,
Robert K. Brayton:
Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing.
ICCAD 1991: 188-191 |
| 28 | | Cho W. Moon,
Paul R. Stephan,
Robert K. Brayton:
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications.
ICCAD 1991: 322-325 |
| 27 | | Hamid Savoj,
Robert K. Brayton,
Hervé J. Touati:
Extracting Local Don't Cares for Network Optimization.
ICCAD 1991: 514-517 |
| 26 | | Hamid Savoj,
Robert K. Brayton:
Observability Relations and Observability Don't Cares.
ICCAD 1991: 518-521 |
| 25 | | Rajeev Murgai,
Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Improved Logic Synthesis Algorithms for Table Look Up Architectures.
ICCAD 1991: 564-567 |
| 24 | | Rajeev Murgai,
Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.
ICCAD 1991: 572-575 |
| 23 | | Rajeev Murgai,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
On Clustering for Minimum Delay/Area.
ICCAD 1991: 6-9 |
| 22 | | Yosinori Watanabe,
Robert K. Brayton:
Incremental Synthesis for Engineering Changes.
ICCD 1991: 40-43 |
| 21 | | Abdul A. Malik,
David Harrison,
Robert K. Brayton:
Three-Level Decomposition with Application to PLDs.
ICCD 1991: 628-633 |
| 20 | | Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Retiming of Circuits with Single Phase Transparent Latches.
ICCD 1991: 86-89 |
| 19 | | Ellen Sentovich,
Robert K. Brayton:
Preserving Don't Care Conditions During Retiming.
VLSI 1991: 461-470 |
| 18 | EE | Sharad Malik,
Ellen M. Sentovich,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Retiming and resynthesis: optimizing sequential networks with combinational techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 74-84 (1991) |
| 17 | EE | Abdul A. Malik,
Robert K. Brayton,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Reduced offsets for minimization of binary-valued functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 413-426 (1991) |
| 1990 |
|---|
| 16 | EE | Patrick C. McGeer,
Robert K. Brayton:
Timing Analysis in Precharge/Unate Networks.
DAC 1990: 124-129 |
| 15 | EE | Abdul A. Malik,
Robert K. Brayton,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Reduced Offsets for Two-Level Multi-Valued Logic Minimization.
DAC 1990: 290-296 |
| 14 | EE | Hamid Savoj,
Robert K. Brayton:
The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks.
DAC 1990: 297-301 |
| 13 | EE | Rajeev Murgai,
Yoshihito Nishizaki,
Narendra V. Shenoy,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Logic Synthesis for Programmable Gate Arrays.
DAC 1990: 620-625 |
| 12 | | Hervé J. Touati,
Hamid Savoj,
Bill Lin,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Implicit State Enumeration of Finite State Machines Using BDDs.
ICCAD 1990: 130-133 |
| 11 | | Sharad Malik,
Kanwar Jit Singh,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Performance Optimization of Pipelined Circuits.
ICCAD 1990: 410-413 |
| 10 | | Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli,
Kwang-Ting Cheng:
Timing Optimization with Testability Considerations.
ICCAD 1990: 460-463 |
| 9 | | Luciano Lavagno,
Sharad Malik,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.
ICCAD 1990: 560-563 |
| 8 | | Arvind Srinivasan,
Timothy Kam,
Sharad Malik,
Robert K. Brayton:
Algorithms for Discrete Function Manipulation.
ICCAD 1990: 92-95 |
| 1989 |
|---|
| 7 | EE | Patrick C. McGeer,
Robert K. Brayton:
Efficient Prime Factorization of Logic Expressions.
DAC 1989: 221-225 |
| 6 | EE | Alexander Saldanha,
Albert R. Wang,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Multi-level Logic Simplification Using Don't Cares and Filters.
DAC 1989: 277-282 |
| 5 | EE | Patrick C. McGeer,
Robert K. Brayton:
Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network.
DAC 1989: 561-567 |
| 1988 |
|---|
| 4 | EE | Karen A. Bartlett,
Robert K. Brayton,
Gary D. Hachtel,
Reily M. Jacoby,
Christopher R. Morrison,
Richard L. Rudell,
Alberto L. Sangiovanni-Vincentelli,
Albert R. Wang:
Multi-level logic minimization using implicit don't cares.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 723-740 (1988) |
| 1987 |
|---|
| 3 | EE | Robert K. Brayton,
Richard L. Rudell,
Alberto L. Sangiovanni-Vincentelli,
Albert R. Wang:
MIS: A Multiple-Level Logic Optimization System.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1062-1081 (1987) |
| 1986 |
|---|
| 2 | EE | Giovanni De Micheli,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Correction to "Optimal State Assignment for Finite State Machines".
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 239-239 (1986) |
| 1985 |
|---|
| 1 | EE | Giovanni De Micheli,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Optimal State Assignment for Finite State Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 269-285 (1985) |
