Chandramouli Visweswariah

2006
23	EE	Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett: First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2170-2180 (2006)
22	EE	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2376-2392 (2006)
2005
21	EE	Andreas Wächter, Chandramouli Visweswariah, Andrew R. Conn: Large-scale nonlinear optimization in circuit tuning. Future Generation Comp. Syst. 21(8): 1251-1262 (2005)
2004
20	EE	Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan: First-order incremental block-based statistical timing analysis. DAC 2004: 331-336
19	EE	Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah: Is statistical timing statistically significant? DAC 2004: 498
2003
18	EE	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical timing for parametric yield prediction of digital integrated circuits. DAC 2003: 932-937
2002
17	EE	Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski: Uncertainty-aware circuit optimization. DAC 2002: 58-63
2001
16	EE	Andrew R. Conn, Chandramouli Visweswariah: Overview of continuous optimization advances and applications to circuit tuning. ISPD 2001: 74-81
2000
15	EE	Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn: Noise considerations in circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 679-690 (2000)
1999
14	EE	Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan: Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. DAC 1999: 452-459
13	EE	Chandramouli Visweswariah, Andrew R. Conn: Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. ICCAD 1999: 244-252
1998
12	EE	Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah: Noise considerations in circuit optimization. ICCAD 1998: 220-227
11	EE	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu: JiffyTune: circuit optimization using time-domain sensitivities. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1292-1309 (1998)
1997
10	EE	Chandramouli Visweswariah: Optimization techniques for high-performance digital circuits. ICCAD 1997: 198-205
9	EE	Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu: Circuit optimization via adjoint Lagrangians. ICCAD 1997: 281-288
1996
8	EE	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah: Optimization of custom MOS circuits by transistor sizing. ICCAD 1996: 174-180
7	EE	Daniel Brand, Chandramouli Visweswariah: Inaccuracies in power estimation during logic synthesis. ICCAD 1996: 388-394
1993
6	EE	Chandramouli Visweswariah, Jalal A. Wehbeh: Incremental Event-Driven Simulation of Digital FET Circuits. DAC 1993: 737-741
1992
5	EE	Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen: M3-a multilevel mixed-mode mixed A/D simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 575-585 (1992)
1991
4	EE	Chandramouli Visweswariah, Ronald A. Rohrer: Efficient Simulation of Bipolar Digital ICs. DAC 1991: 32-37
3	EE	Chandramouli Visweswariah, Ronald A. Rohrer: Piecewise approximate circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 861-870 (1991)
1990
2		Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer: Incorporation of Inductors in Piecewise Approximate Circuit Simulation. ICCAD 1990: 162-165
1988
1	EE	Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen: Model Development and Verification for High Level Analog Blocks. DAC 1988: 376-382

Coauthor Index

1	Xiaoliang Bai	[17]
2	Daniel K. Beece	[23]
3	Clive Bittlestone	[19]
4	Ahsan Bootehsaz	[19]
5	Shekhar Y. Borkar (Shekhar Borkar)	[19]
6	Daniel Brand	[7]
7	Rakesh Chadha	[1] [5]
8	Chin-Fu Chen	[1] [5]
9	E. Chen	[19]
10	Andrew R. Conn	[8] [9] [11] [12] [13] [14] [15] [16] [21]
11	Paula K. Coulman	[8] [11]
12	Ibrahim M. Elfadel	[14]
13	Peter Feldmann	[2]
14	Richard Goldman	[19]
15	Ruud A. Haring	[8] [9] [11] [12] [15]
16	Jeffrey G. Hemmett	[23]
17	Jochen A. G. Jess	[18] [22]
18	K. Kalafala	[18] [20] [22] [23]
19	Kurt Keutzer	[19]
20	W. W. Molzen	[14]
21	Gregory L. Morrill	[8] [11]
22	Srinath R. Naidu	[18] [22]
23	S. Narayan	[20] [23]
24	P. R. O'Brien	[14]
25	Ralph H. J. M. Otten	[18] [22]
26	J. Piaget	[23]
27	K. Ravindran	[20] [23]
28	Ronald A. Rohrer	[2] [3] [4]
29	Louis Scheffer	[19]
30	Philip N. Strenski	[14] [17]
31	N. Venkateswaran	[23]
32	Andreas Wächter	[21]
33	Steven G. Walker	[20] [23]
34	Jalal A. Wehbeh	[6]
35	C. B. Whan	[14]
36	Chai Wah Wu	[9] [11]

Colors in the list of coauthors