Philippe Maurine

2008
42	EE	Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert: A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. DELTA 2008: 107-110
41	EE	Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert: Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. ISVLSI 2008: 310-315
40	EE	Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard: Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321
39	EE	Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres: Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. PATMOS 2008: 229-236
38	EE	Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198
37	EE	Nadine Azémard, Philippe Maurine, Johan Vounckx: Editorial. Integration 41(1): 1 (2008)
2007
36	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature and voltage aware timing analysis: application to voltage drops. DATE 2007: 1012-1017
35	EE	V. Migairou, Robin Wilson, S. Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147
34	EE	Alin Razafindraibe, Michel Robert, Philippe Maurine: Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. PATMOS 2007: 340-351
33	EE	Alin Razafindraibe, Philippe Maurine: A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. PATMOS 2007: 394-403
32	EE	Alin Razafindraibe, Michel Robert, Philippe Maurine: Improvement of dual rail logic as a countermeasure against DPA. VLSI-SoC 2007: 270-275
31	EE	Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol CoRR abs/0710.4760: (2007)
30	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 801-815 (2007)
2006
29		Johan Vounckx, Nadine Azémard, Philippe Maurine: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings Springer 2006
28	EE	Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Circuit sizing method under delay constraint. ISCAS 2006
27	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Timing analysis in presence of supply voltage and temperature variations. ISPD 2006: 10-16
26	EE	V. Migairou, Robin Wilson, S. Engels, Nadine Azémard, Philippe Maurine: Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476
25	EE	Alin Razafindraibe, Michel Robert, Philippe Maurine: Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. PATMOS 2006: 634-644
24	EE	Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin: Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186
23	EE	B. Lasbouygues, S. Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)
22	EE	S. Engels, Robin Wilson, Nadine Azémard, Philippe Maurine: A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integration 39(4): 433-456 (2006)
2005
21	EE	Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645
20	EE	Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine: A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580
19	EE	Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Speed Indicators for Circuit Optimization. PATMOS 2005: 618-628
18	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature Dependency in UDSM Process. PATMOS 2005: 693-703
17	EE	Alin Razafindraibe, Michel Robert, Philippe Maurine: Compact and Secured Primitives for the Design of Asynchronous Circuits. J. Low Power Electronics 1(1): 20-26 (2005)
2004
16		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192
15	EE	Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109
14	EE	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118
13	EE	A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731
12	EE	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848
2003
11	EE	Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191
10	EE	Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460
9	EE	Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69
2002
8	EE	Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330
7	EE	Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257
6	EE	Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)
2001
5	EE	Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Output transition time modeling of CMOS structures. ISCAS (5) 2001: 363-366
4		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
3		Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
2000
2	EE	Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS 2000: 129-138
1	EE	Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne: Second Generation Delay Model for Submicron CMOS Process. PATMOS 2000: 159-167

Coauthor Index

1	M. Aline	[3]
2	Daniel Auvergne	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [21] [23] [31]
3	Nadine Azémard (Nadine Azémard-Crestani)	[3] [4] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [18] [19] [21] [22] [23] [26] [27] [28] [29] [30] [31] [35] [36] [37] [40]
4	Magali Bastian	[41] [42]
5	Marc Belleville	[40]
6	Christian Bernard	[40]
7	G. Fraidy Bouesse	[11]
8	Ney Laert Vilar Calazans (Ney Calazans)	[38]
9	S. Engels	[22] [23] [26] [35]
10	A. Landrault	[13] [19] [28]
11	B. Lasbouygues	[12] [14] [18] [23] [27] [30] [36]
12	Mathieu Lisart	[39]
13	Victor Lomné	[38]
14	Xavier Michel	[8] [9] [10] [15] [16] [21] [31]
15	V. Migairou	[26] [35]
16	Michael Yap San Min	[41] [42]
17	Thomas Ordas	[39]
18	Alin Razafindraibe	[17] [20] [24] [25] [32] [33] [34]
19	Bettina Rebaud	[40]
20	Marc Renaudin	[11] [20] [24]
21	Mustapha Rezzoug	[1] [2] [5] [6]
22	Jean-Baptiste Rigaud	[11]
23	Michel Robert	[13] [17] [20] [24] [25] [32] [34] [38] [40] [41] [42]
24	Etienne Sicard	[39]
25	Gilles Sicard	[11]
26	Rafael Soares	[38]
27	Lionel Torres	[38] [39]
28	Alexandre Verle	[9] [10] [15] [16] [19] [21] [28] [31]
29	Johan Vounckx	[29] [37]
30	Robin Wilson	[12] [14] [18] [22] [23] [26] [27] [30] [35] [36]
31	Zequin Wu	[35] [40]