2009 | ||
---|---|---|
132 | EE | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang: An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 98-110 (2009) |
131 | EE | Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang: A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 193-206 (2009) |
2008 | ||
130 | EE | Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang: Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. DAC 2008: 167-172 |
129 | EE | Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289 |
128 | EE | Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang: Predictive formulae for OPC with applications to lithography-friendly routing. DAC 2008: 510-515 |
127 | EE | Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang: Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD 2008: 218-223 |
126 | EE | Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang: Multi-layer global routing considering via and wire capacities. ICCAD 2008: 350-355 |
125 | EE | Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang: Routing for chip-package-board co-design considering differential pairs. ICCAD 2008: 512-517 |
124 | EE | Jia-Wei Fang, Yao-Wen Chang: Area-I/O flip-chip routing for chip-package co-design. ICCAD 2008: 518-522 |
123 | EE | Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38 |
122 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1928-1941 (2008) |
121 | EE | Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang: Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2007-2016 (2008) |
120 | EE | Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2145-2155 (2008) |
119 | EE | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin: A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 286-294 (2008) |
118 | EE | Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 643-653 (2008) |
117 | EE | Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: Effective Wire Models for X-Architecture Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 654-658 (2008) |
116 | EE | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Full-Chip Routing Considering Double-Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 844-857 (2008) |
115 | EE | Zhe-Wei Jiang, Yao-Wen Chang: An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1055-1065 (2008) |
114 | EE | Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1228-1240 (2008) |
113 | EE | Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen: An Efficient Graph-Based Algorithm for ESD Current Path Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1363-1375 (2008) |
112 | EE | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu: MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1621-1634 (2008) |
2007 | ||
111 | EE | Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang: Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243 |
110 | EE | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu: MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC 2007: 447-452 |
109 | EE | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang: An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. DAC 2007: 606-611 |
108 | EE | Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang: A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. DAC 2007: 887-890 |
107 | EE | I-Jye Lin, Yao-Wen Chang: An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. ICCAD 2007: 119-124 |
106 | EE | Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang: Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. ICCAD 2007: 380-385 |
105 | EE | Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang: ECO timing optimization using spare cells. ICCAD 2007: 530-535 |
104 | EE | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ICCAD 2007: 650-655 |
103 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757 |
102 | EE | Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang: Novel wire density driven full-chip routing for CMP variation control. ICCAD 2007: 831-838 |
101 | EE | Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen: 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9 |
100 | EE | Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97 |
99 | EE | Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134 |
98 | EE | Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: X-architecture placement based on effective wire models. ISPD 2007: 87-94 |
97 | EE | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang: A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS 2007: 148-159 |
96 | EE | I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang: Statistical circuit optimization considering device andinterconnect process variations. SLIP 2007: 47-54 |
95 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
94 | EE | Bor-Yiing Su, Yao-Wen Chang: An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1818-1829 (2007) |
93 | EE | Chen-Wei Liu, Yao-Wen Chang: Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 693-704 (2007) |
92 | EE | Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 719-733 (2007) |
91 | EE | Tai-Chen Chen, Yao-Wen Chang: Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1041-1053 (2007) |
90 | EE | Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang: A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1417-1429 (2007) |
89 | EE | Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang: MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1430-1444 (2007) |
88 | EE | Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1625-1636 (2007) |
87 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. JETC 3(3): (2007) |
2006 | ||
86 | EE | Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang: Simultaneous block and I/O buffer floorplanning for flip-chip design. ASP-DAC 2006: 213-218 |
85 | EE | Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen: IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371 |
84 | EE | Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin: A novel framework for multilevel full-chip gridless routing. ASP-DAC 2006: 636-641 |
83 | EE | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Novel full-chip gridless routing considering double-via insertion. DAC 2006: 755-760 |
82 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934 |
81 | EE | Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD 2006: 187-192 |
80 | EE | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: Voltage island aware floorplanning for power and timing optimization. ICCAD 2006: 389-394 |
79 | EE | Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo: Current path analysis for electrostatic discharge protection. ICCAD 2006: 510-515 |
78 | EE | Zhe-Wei Jiang, Yao-Wen Chang: An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. ICCAD 2006: 669-674 |
77 | EE | Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai: Inductance extraction for general interconnect structures. ISCAS 2006 |
76 | EE | Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD 2006: 215-217 |
75 | EE | Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63 |
74 | EE | Chen-Wei Liu, Yao-Wen Chang: Floorplan and power/ground network co-synthesis for fast design convergence. ISPD 2006: 86-93 |
73 | EE | Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006) |
72 | EE | Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen: IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2513-2525 (2006) |
71 | EE | Tung-Chieh Chen, Yao-Wen Chang: Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 637-650 (2006) |
70 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with jumper insertion for antenna avoidance. Integration 39(4): 420-432 (2006) |
2005 | ||
69 | EE | Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang: Placement with symmetry constraints for analog layout design using TCG-S. ASP-DAC 2005: 1135-1137 |
68 | EE | Tai-Chen Chen, Yao-Wen Chang: Multilevel full-chip gridless routing considering optical proximity correction. ASP-DAC 2005: 1160-1163 |
67 | EE | Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang: SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC 2005: 1188-1191 |
66 | EE | Bor-Yiing Su, Yao-Wen Chang: An exact jumper insertion algorithm for antenna effect avoidance/fixing. DAC 2005: 325-328 |
65 | EE | Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen: Multilevel full-chip routing for the X-based architecture. DAC 2005: 597-602 |
64 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin: IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD 2005: 159-164 | |
63 | Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang: A routing algorithm for flip-chip design. ICCAD 2005: 753-758 | |
62 | EE | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137 |
61 | EE | Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang: Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126 |
60 | EE | Tung-Chieh Chen, Yao-Wen Chang: Modern floorplanning based on fast simulated annealing. ISPD 2005: 104-112 |
59 | EE | Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang: NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD 2005: 236-238 |
58 | EE | Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen: Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486 |
57 | EE | Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen: Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36 |
56 | EE | Jai-Ming Lin, Yao-Wen Chang: TCG: A transitive closure graph-based representation for general floorplans. IEEE Trans. VLSI Syst. 13(2): 288-292 (2005) |
55 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 869-878 (2005) |
2004 | ||
54 | EE | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273 |
53 | EE | Yi-Hui Cheng, Yao-Wen Chang: Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. ASP-DAC 2004: 624-627 |
52 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen: Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730 |
51 | EE | Su-Wei Wu, Yao-Wen Chang: Efficient power/ground network analysis for power integrity-driven design methodology. DAC 2004: 177-180 |
50 | EE | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305 |
49 | EE | Meng-Chen Wu, Yao-Wen Chang: Placement with Alignment and Performance Constraints Using the B*-Tree Representation. ICCD 2004: 568-571 |
48 | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948 | |
47 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with antenna avoidance. ISPD 2004: 34-40 |
46 | Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang: Timing modeling and optimization under the transmission line model. IEEE Trans. VLSI Syst. 12(1): 28-41 (2004) | |
45 | EE | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao: Simultaneous floor plan and buffer-block optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004) |
44 | EE | Yao-Wen Chang, Shih-Ping Lin: MR: a new framework for multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 793-800 (2004) |
43 | EE | Jai-Ming Lin, Yao-Wen Chang: TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 968-980 (2004) |
42 | EE | Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang: A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integration 38(2): 245-265 (2004) |
2003 | ||
41 | EE | Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang: Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817 |
40 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD 2003: 382-387 |
39 | EE | Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong: Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003) |
38 | EE | Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang: Rectilinear block placement using B*-trees. ACM Trans. Design Autom. Electr. Syst. 8(2): 188-202 (2003) |
37 | EE | Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin: Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. VLSI Syst. 11(4): 679-686 (2003) |
2002 | ||
36 | EE | Jai-Ming Lin, Yao-Wen Chang: TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. DAC 2002: 842-847 |
35 | EE | Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang: Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. DATE 2002: 69-77 |
34 | EE | Shih-Ping Lin, Yao-Wen Chang: A novel framework for multilevel routing considering routability and performance. ICCAD 2002: 44-50 |
33 | EE | Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang: Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ISQED 2002: 523-528 |
32 | EE | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: Performance-driven placement for dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 628-642 (2002) |
31 | EE | Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang: Comment on Generic Universal Switch Blocks. IEEE Trans. Computers 51(1): 93-96 (2002) |
30 | EE | Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang: Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. IEEE Trans. VLSI Syst. 10(6): 886-901 (2002) |
2001 | ||
29 | EE | Jai-Ming Lin, Yao-Wen Chang: TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. DAC 2001: 764-769 |
28 | Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang: Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. ICCD 2001: 192-198 | |
27 | Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang: Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD 2001: 335-347 | |
26 | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: An Algorithm for Dynamically Reconfigurable FPGA Placement. ICCD 2001: 501-504 | |
25 | EE | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1266-1274 (2001) |
24 | EE | Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong: Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 784-791 (2001) |
2000 | ||
23 | EE | Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu: B*-Trees: a new representation for non-slicing floorplans. DAC 2000: 458-463 |
22 | EE | Yao-Wen Chang, Yu-Tsang Chang: An architecture-driven metric for simultaneous placement and global routing for FPGAs. DAC 2000: 567-572 |
21 | EE | Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang: Rectilinear Block Placement Using B*-Trees. ICCD 2000: 351-356 |
20 | EE | Song-Ra Pan, Yao-Wen Chang: Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. ICCD 2000: 581-584 |
19 | EE | Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133 |
18 | EE | Yao-Wen Chang, Kai Zhu, D. F. Wong: Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000) |
17 | EE | Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang: Generic Universal Switch Blocks. IEEE Trans. Computers 49(4): 348-359 (2000) |
16 | EE | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou: Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000) |
1999 | ||
15 | EE | Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang: Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95 |
14 | EE | Guang-Ming Wu, Michael Shyu, Yao-Wen Chang: Universal Switch Blocks for Three-Dimensional FPGA Design. FPGA 1999: 254 |
13 | EE | Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang: A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD 1999: 364-369 |
12 | EE | Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang: Generic Universal Switch Blocks. ICCD 1999: 311-314 |
11 | Guang-Ming Wu, Yao-Wen Chang: Quasi-Universal Switch Matrices for FPD Design. IEEE Trans. Computers 48(10): 1107-1122 (1999) | |
1998 | ||
10 | EE | Yao-Wen Chang, Jai-Ming Lin, D. F. Wong: Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39 |
9 | EE | Guang-Ming Wu, Yao-Wen Chang: Switch-matrix architecture and routing for FPDs. ISPD 1998: 158-163 |
1997 | ||
8 | EE | Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan: Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 32-46 (1997) |
1996 | ||
7 | EE | Chung-Ping Chen, Yao-Wen Chang, D. F. Wong: Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408 |
6 | EE | Yao-Wen Chang, D. F. Wong, C. K. Wong: Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA 1996: 80-86 |
5 | EE | Yao-Wen Chang, D. F. Wong, C. K. Wong: Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1(1): 80-101 (1996) |
1995 | ||
4 | EE | Yao-Wen Chang, D. F. Wong, C. K. Wong: FPGA global routing based on a new congestion metric. ICCD 1995: 372- |
3 | EE | Yao-Wen Chang, D. F. Wong, C. K. Wong: Design and analysis of FPGA/FPIC switch modules. ICCD 1995: 394-401 |
1994 | ||
2 | EE | Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong: A new global routing algorithm for FPGAs. ICCAD 1994: 356-361 |
1993 | ||
1 | EE | Kai Zhu, D. F. Wong, Yao-Wen Chang: Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485 |