| 2008 |
|---|
| 12 | EE | Pallav Gupta,
Rui Zhang,
Niraj K. Jha:
Automatic Test Generation for Combinational Threshold Logic Networks.
IEEE Trans. VLSI Syst. 16(8): 1035-1045 (2008) |
| 2007 |
|---|
| 11 | EE | Pallav Gupta,
Niraj K. Jha,
Loganathan Lingappan:
A Test Generation Framework for Quantum Cellular Automata Circuits.
IEEE Trans. VLSI Syst. 15(1): 24-36 (2007) |
| 10 | EE | Rui Zhang,
Pallav Gupta,
Niraj K. Jha:
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1233-1245 (2007) |
| 2006 |
|---|
| 9 | EE | Pallav Gupta,
Niraj K. Jha,
Loganathan Lingappan:
Test generation for combinational quantum cellular automata (QCA) circuits.
DATE 2006: 311-316 |
| 8 | EE | Pallav Gupta,
Abhinav Agrawal,
Niraj K. Jha:
An Algorithm for Synthesis of Reversible Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2317-2330 (2006) |
| 2005 |
|---|
| 7 | EE | Pallav Gupta,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems.
DAC 2005: 244-247 |
| 6 | EE | Rui Zhang,
Pallav Gupta,
Niraj K. Jha:
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.
VLSI Design 2005: 229-234 |
| 5 | EE | Rui Zhang,
Pallav Gupta,
Lin Zhong,
Niraj K. Jha:
Threshold network synthesis and optimization and its application to nanotechnologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 107-118 (2005) |
| 2004 |
|---|
| 4 | EE | Rui Zhang,
Pallav Gupta,
Lin Zhong,
Niraj K. Jha:
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.
DATE 2004: 904-909 |
| 3 | EE | Pallav Gupta,
Niraj K. Jha:
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.
DATE 2004: 974-979 |
| 2 | EE | Pallav Gupta,
Rui Zhang,
Niraj K. Jha:
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.
ICCD 2004: 540-543 |
| 2003 |
|---|
| 1 | EE | Pallav Gupta,
Lin Zhong,
Niraj K. Jha:
A High-level Interconnect Power Model for Design Space Exploration.
ICCAD 2003: 551-559 |
