| 2008 |
|---|
| 11 | EE | Alan Mishchenko,
Robert K. Brayton,
Satrajit Chatterjee:
Boolean factoring and decomposition of logic networks.
ICCAD 2008: 38-44 |
| 2007 |
|---|
| 10 | EE | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton,
Andreas Kuehlmann:
On Resolution Proofs for Combinational Equivalence.
DAC 2007: 600-605 |
| 9 | EE | Alan Mishchenko,
Sungmin Cho,
Satrajit Chatterjee,
Robert K. Brayton:
Combinational and sequential mapping with priority cuts.
ICCAD 2007: 354-361 |
| 8 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton:
Improvements to Technology Mapping for LUT-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 240-253 (2007) |
| 2006 |
|---|
| 7 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton:
DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
DAC 2006: 532-535 |
| 6 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton:
Improvements to technology mapping for LUT-based FPGAs.
FPGA 2006: 41-49 |
| 5 | EE | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton:
Factor cuts.
ICCAD 2006: 143-150 |
| 4 | EE | Alan Mishchenko,
Satrajit Chatterjee,
Robert K. Brayton,
Niklas Eén:
Improvements to combinational equivalence checking.
ICCAD 2006: 836-843 |
| 3 | EE | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton,
Xinning Wang,
Timothy Kam:
Reducing Structural Bias in Technology Mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2894-2903 (2006) |
| 2005 |
|---|
| 2 | | Satrajit Chatterjee,
Alan Mishchenko,
Robert K. Brayton,
Xinning Wang,
Timothy Kam:
Reducing structural bias in technology mapping.
ICCAD 2005: 519-526 |
| 2004 |
|---|
| 1 | EE | Satrajit Chatterjee,
Robert K. Brayton:
A new incremental placement algorithm and its application to congestion-aware divisor extraction.
ICCAD 2004: 541-548 |
