| 2008 |
|---|
| 86 | EE | Kalliopi Tsota,
Cheng-Kok Koh,
Venkataramanan Balakrishnan:
Guiding global placement with wire density.
ICCAD 2008: 212-217 |
| 85 | EE | Jitesh Jain,
Hong Li,
Cheng-Kok Koh,
Venkataramanan Balakrishnan:
A fast band matching technique for impedance extraction.
ISCAS 2008: 2981-2984 |
| 84 | EE | Kuang-Yao Lee,
Cheng-Kok Koh,
Ting-Chi Wang,
Kai-Yuan Chao:
Optimal post-routing redundant via insertion.
ISPD 2008: 111-117 |
| 83 | EE | Kuang-Yao Lee,
Cheng-Kok Koh,
Ting-Chi Wang,
Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008) |
| 2007 |
|---|
| 82 | EE | Ruilin Wang,
Cheng-Kok Koh:
A frequency-domain technique for statistical timing analysis of clock meshes.
ICCAD 2007: 334-339 |
| 81 | EE | Hong Li,
Jitesh Jain,
Cheng-Kok Koh,
Venkataramanan Balakrishnan:
A fast band-matching technique for interconnect inductance modeling.
ICCAD 2007: 568-571 |
| 80 | EE | Weng-Fai Wong,
Cheng-Kok Koh,
Yiran Chen,
Hai Li:
VOSCH: Voltage scaled cache hierarchies.
ICCD 2007: 496-503 |
| 79 | EE | Yiran Chen,
Hai Li,
Jing Li,
Cheng-Kok Koh:
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
ISLPED 2007: 195-200 |
| 78 | EE | Hong Li,
Cheng-Kok Koh,
Venkataramanan Balakrishnan,
Yiran Chen:
Statistical Timing Analysis Considering Spatial Correlations.
ISQED 2007: 102-107 |
| 77 | EE | Hong Li,
Jitesh Jain,
Venkataramanan Balakrishnan,
Cheng-Kok Koh:
Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization.
ISQED 2007: 627-632 |
| 76 | EE | Chen Li,
Cheng-Kok Koh:
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement.
ISQED 2007: 829-834 |
| 75 | EE | Ruibing Lu,
Aiqun Cao,
Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
IEEE Trans. VLSI Syst. 15(1): 69-79 (2007) |
| 74 | EE | Chen Li,
Min Xie,
Cheng-Kok Koh,
Jason Cong,
Patrick H. Madden:
Routability-Driven Placement and White Space Allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 858-871 (2007) |
| 2006 |
|---|
| 73 | EE | Hai Li,
Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
ASP-DAC 2006: 158-163 |
| 72 | EE | Jitesh Jain,
Stephen Cauley,
Cheng-Kok Koh,
Venkataramanan Balakrishnan:
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices.
ASP-DAC 2006: 422-427 |
| 71 | EE | Ya-Chi Yang,
Cheng-Kok Koh,
Venkataramanan Balakrishnan:
Adaptive admittance-based conductor meshing for interconnect analysis.
ASP-DAC 2006: 509-514 |
| 70 | EE | Hong Li,
Venkataramanan Balakrishnan,
Cheng-Kok Koh:
Stable and compact inductance modeling of 3-D interconnect structures.
ICCAD 2006: 1-6 |
| 69 | EE | Aiqun Cao,
Ruibing Lu,
Chen Li,
Cheng-Kok Koh:
Postlayout optimization for synthesis of Domino circuits.
ACM Trans. Design Autom. Electr. Syst. 11(4): 797-821 (2006) |
| 68 | EE | Ruibing Lu,
Cheng-Kok Koh:
Performance analysis of latency-insensitive systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 469-483 (2006) |
| 2005 |
|---|
| 67 | EE | Jacob R. Minz,
Sung Kyu Lim,
Cheng-Kok Koh:
3D module placement for congestion and power noise reduction.
ACM Great Lakes Symposium on VLSI 2005: 458-461 |
| 66 | EE | Ruibing Lu,
Aiqun Cao,
Cheng-Kok Koh:
Improving the scalability of SAMBA bus architecture.
ASP-DAC 2005: 1164-1167 |
| 65 | EE | Aiqun Cao,
Ruibing Lu,
Cheng-Kok Koh:
Post-layout logic duplication for synthesis of domino circuits with complex gates.
ASP-DAC 2005: 260-265 |
| 64 | EE | Chen Li,
Cheng-Kok Koh,
Patrick H. Madden:
Floorplan management: incremental placement for gate sizing and buffer insertion.
ASP-DAC 2005: 349-354 |
| 63 | EE | Hong Li,
Venkataramanan Balakrishnan,
Cheng-Kok Koh,
Guoan Zhong:
Compact and stable modeling of partial inductance and reluctance matrices.
ASP-DAC 2005: 507-510 |
| 62 | EE | Wai-Ching Douglas Lam,
Cheng-Kok Koh:
Process variation robust clock tree routing.
ASP-DAC 2005: 606-611 |
| 61 | EE | Yongxin Zhu,
Weng-Fai Wong,
Cheng-Kok Koh:
A Performance and Power Co-optimization Approach for Modern Processors.
CIT 2005: 822-828 |
| 60 | | Wai-Ching Douglas Lam,
J. Jam,
Cheng-Kok Koh,
Venkataramanan Balakrishnan,
Yiran Chen:
Statistical based link insertion for robust clock network design.
ICCAD 2005: 588-591 |
| 59 | EE | Yiran Chen,
Hai Li,
Kaushik Roy,
Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
ISLPED 2005: 115-118 |
| 58 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) |
| 57 | EE | Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
IEEE Trans. VLSI Syst. 13(1): 75-85 (2005) |
| 56 | EE | Ameya R. Agnihotri,
Satoshi Ono,
Chen Li,
Mehmet Can Yildiz,
Ateen Khatkhate,
Cheng-Kok Koh,
Patrick H. Madden:
Mixed block placement via fractional cut recursive bisection.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 748-761 (2005) |
| 2004 |
|---|
| 55 | EE | Ruibing Lu,
Cheng-Kok Koh:
A high performance bus communication architecture through bus splitting.
ASP-DAC 2004: 751-755 |
| 54 | EE | Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
ASP-DAC 2004: 893-898 |
| 53 | EE | Ngai Wong,
Venkataramanan Balakrishnan,
Cheng-Kok Koh:
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme.
DAC 2004: 369-374 |
| 52 | EE | Aiqun Cao,
Cheng-Kok Koh:
Post-layout logic optimization of domino circuits.
DAC 2004: 820-825 |
| 51 | EE | Chen Li,
Min Xie,
Cheng-Kok Koh,
Jason Cong,
Patrick H. Madden:
Routability-driven placement and white space allocation.
ICCAD 2004: 394-401 |
| 50 | EE | Jitesh Jain,
Cheng-Kok Koh,
Venkataramanan Balakrishnan:
Fast simulation of VLSI interconnects.
ICCAD 2004: 93-98 |
| 49 | EE | Ateen Khatkhate,
Chen Li,
Ameya R. Agnihotri,
Mehmet Can Yildiz,
Satoshi Ono,
Cheng-Kok Koh,
Patrick H. Madden:
Recursive bisection based mixed block placement.
ISPD 2004: 84-89 |
| 2003 |
|---|
| 48 | EE | Guoan Zhong,
Cheng-Kok Koh,
Venkataramanan Balakrishnan,
Kaushik Roy:
An adaptive window-based susceptance extraction and its efficient implementation.
DAC 2003: 728-731 |
| 47 | EE | Ruibing Lu,
Cheng-Kok Koh:
Interconnect Planning with Local Area Constrained Retiming.
DATE 2003: 10442-10447 |
| 46 | EE | Ruibing Lu,
Cheng-Kok Koh:
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels.
ICCAD 2003: 227-231 |
| 45 | EE | Ruibing Lu,
Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
ICCAD 2003: 8-12 |
| 44 | EE | Aiqun Cao,
Cheng-Kok Koh:
Non-Crossing OBDDs for Mapping to Regular Circuit Structures.
ICCD 2003: 338-343 |
| 43 | EE | Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
ISLPED 2003: 229-234 |
| 42 | EE | Wai-Ching Douglas Lam,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy.
ISQED 2003: 327-332 |
| 41 | EE | Guoan Zhong,
Cheng-Kok Koh,
Kaushik Roy:
On-chip interconnect modeling by wire duplication.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1521-1532 (2003) |
| 2002 |
|---|
| 40 | EE | Q. Su,
Venkataramanan Balakrishnan,
Cheng-Kok Koh:
A factorization-based framework for passivity-preserving model reduction of RLC systems.
DAC 2002: 40-45 |
| 39 | EE | Ruibing Lu,
Guoan Zhong,
Cheng-Kok Koh,
Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning.
DATE 2002: 690-695 |
| 38 | EE | Yiran Chen,
Venkataramanan Balakrishnan,
Cheng-Kok Koh,
Kaushik Roy:
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.
DATE 2002: 931-937 |
| 37 | EE | Guoan Zhong,
Cheng-Kok Koh,
Kaushik Roy:
On-chip interconnect modeling by wire duplication.
ICCAD 2002: 341-346 |
| 36 | EE | Guoan Zhong,
Cheng-Kok Koh:
Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects.
ICCD 2002: 428-433 |
| 35 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits.
ISQED 2002: 229-234 |
| 34 | EE | Wai-Ching Douglas Lam,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Power Supply Noise Suppression via Clock Skew Scheduling.
ISQED 2002: 355-360 |
| 33 | EE | Q. Su,
Venkataramanan Balakrishnan,
Cheng-Kok Koh:
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods.
VLSI Design 2002: 311-316 |
| 32 | EE | Shiyou Zhao,
Kaushik Roy,
Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.
VLSI Design 2002: 489- |
| 31 | EE | Chung-Wen Albert Tsao,
Cheng-Kok Koh:
UST/DME: a clock tree router for general skew constraints.
ACM Trans. Design Autom. Electr. Syst. 7(3): 359-379 (2002) |
| 30 | EE | Shiyou Zhao,
Kaushik Roy,
Cheng-Kok Koh:
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 81-92 (2002) |
| 2001 |
|---|
| 29 | | Kaushik Roy,
Sung-Mo Kang,
Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001
ACM 2001 |
| 28 | EE | Rongtian Zhang,
Kaushik Roy,
Cheng-Kok Koh,
David B. Janes:
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration.
DAC 2001: 846-851 |
| 27 | EE | Probir Sarkar,
Cheng-Kok Koh:
Repeater block planning under simultaneous delay and transition time constraints.
DATE 2001: 540-545 |
| 26 | EE | Rongtian Zhang,
Kaushik Roy,
Cheng-Kok Koh,
David B. Janes:
Power trends and performance characterization of 3-dimensional integration.
ISCAS (4) 2001: 414-417 |
| 25 | EE | Rui Wang,
Kaushik Roy,
Cheng-Kok Koh:
Short-circuit power analysis of an inverter driving an RLC load.
ISCAS (4) 2001: 886-889 |
| 24 | EE | Naran Sirisantana,
Aiqun Cao,
Shawn Davidson,
Cheng-Kok Koh,
Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
ISLPED 2001: 267-270 |
| 23 | EE | Shiyou Zhao,
Kaushik Roy,
Cheng-Kok Koh:
Decoupling capacitance allocation for power supply noise suppression.
ISPD 2001: 66-71 |
| 22 | EE | Rongtian Zhang,
Kaushik Roy,
Cheng-Kok Koh,
David B. Janes:
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations.
ISQED 2001: 217-222 |
| 21 | EE | Jason Cong,
Cheng-Kok Koh,
Patrick H. Madden:
Interconnect layout optimization under higher order RLC model forMCM designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1455-1463 (2001) |
| 20 | EE | Probir Sarkar,
Cheng-Kok Koh:
Routability-driven repeater block planning for interconnect-centricfloorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 660-671 (2001) |
| 19 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001) |
| 2000 |
|---|
| 18 | EE | Cheng-Kok Koh,
Patrick H. Madden:
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures.
ACM Great Lakes Symposium on VLSI 2000: 47-52 |
| 17 | | Rongtian Zhang,
Kaushik Roy,
Cheng-Kok Koh,
David B. Janes:
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits.
ICCAD 2000: 208-213 |
| 16 | | Chung-Wen Albert Tsao,
Cheng-Kok Koh:
UST/DME: A Clock Tree Router for General Skew Constraints.
ICCAD 2000: 400-405 |
| 15 | | Guoan Zhong,
Cheng-Kok Koh,
Kaushik Roy:
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise.
ICCAD 2000: 406-411 |
| 14 | | Shiyou Zhao,
Kaushik Roy,
Cheng-Kok Koh:
Frequency Domain Analysis of Switching Noise on Power Supply Network.
ICCAD 2000: 487-492 |
| 13 | EE | Alexandre Solomatnikov,
Kaushik Roy,
Cheng-Kok Koh,
Dinesh Somasekhar:
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.
ICCD 2000: 241-246 |
| 12 | EE | Shiyou Zhao,
Kaushik Roy,
Cheng-Kok Koh:
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.
ICCD 2000: 65-72 |
| 11 | EE | Probir Sarkar,
Vivek Sundararaman,
Cheng-Kok Koh:
Routability-driven repeater block planning for interconnect-centric floorplanning.
ISPD 2000: 186-191 |
| 1998 |
|---|
| 10 | EE | Jason Cong,
Andrew B. Kahng,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing.
ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) |
| 1997 |
|---|
| 9 | EE | Jason Cong,
David Zhigang Pan,
Lei He,
Cheng-Kok Koh,
Kei-Yong Khoo:
Interconnect design for deep submicron ICs.
ICCAD 1997: 478-485 |
| 8 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance.
ICCAD 1997: 628-633 |
| 7 | EE | Jason Cong,
Cheng-Kok Koh:
Interconnect layout optimization under higher-order RLC model.
ICCAD 1997: 713-720 |
| 1996 |
|---|
| 6 | EE | Jason Cong,
Cheng-Kok Koh,
Kwok-Shing Leung:
Simultaneous buffer and wire sizing for performance and power optimization.
ISLPED 1996: 271-276 |
| 5 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
Patrick H. Madden:
Performance optimization of VLSI interconnect layout.
Integration 21(1-2): 1-94 (1996) |
| 1995 |
|---|
| 4 | EE | Jason Cong,
Andrew B. Kahng,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay.
ICCAD 1995: 66-71 |
| 3 | | Jason Cong,
Cheng-Kok Koh:
Minimum-Cost Bounded-Skew Clock Routing.
ISCAS 1995: 215-218 |
| 1994 |
|---|
| 2 | EE | Jason Cong,
Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization.
ICCAD 1994: 206-212 |
| 1 | EE | Jason Cong,
Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization.
IEEE Trans. VLSI Syst. 2(4): 408-425 (1994) |
