Mark Zwolinski

2008
33	EE	Karthik Baddam, Mark Zwolinski: Divided Backend Duplication Methodology for Balanced Dual Rail Routing. CHES 2008: 396-410
32	EE	Arash Ahmadi, Mark Zwolinski: Symbolic noise analysis approach to computational hardware optimization. DAC 2008: 391-396
2007
31	EE	Xiaoxuan She, Mark Zwolinski: A novel self-routing reconfigurable fault-tolerant cell array. AHS 2007: 725-731
30	EE	Arash Ahmadi, Mark Zwolinski: Multiple-Width Bus Partitioning Approach to Datapath Synthesis. ISCAS 2007: 2994-2997
29	EE	Karthik Baddam, Mark Zwolinski: Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure. VLSI Design 2007: 854-862
2006
28	EE	Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod: Dynamic Voltage Scaling Aware Delay Fault Testing. European Test Symposium 2006: 15-20
27	EE	Himanshu Thapliyal, Mark Zwolinski: Reversible Logic to Cryptographic Hardware: A New Paradigm CoRR abs/cs/0610089: (2006)
26	EE	Petros Oikonomakos, Mark Zwolinski: On the Design of Self-Checking Controllers with Datapath Interactions. IEEE Trans. Computers 55(11): 1423-1434 (2006)
25	EE	Petros Oikonomakos, Mark Zwolinski: An Integrated High-Level On-Line Test Synthesis Tool. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2479-2491 (2006)
24	EE	Vanco B. Litovski, Miona Andrejevic, Mark Zwolinski: Analogue electronic circuit diagnosis based on ANNs. Microelectronics Reliability 46(8): 1382-1391 (2006)
2005
23	EE	Vanco B. Litovski, Mark Zwolinski, Miona Andrejevic: Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs. ISCAS (5) 2005: 5182-5185
2004
22		Mark Zwolinski, Andrew D. Brown: Behavioural modelling of analogue faults in VHDL-AMS - a case study. ISCAS (5) 2004: 632-635
21	EE	M. S. Gaur, Mark Zwolinski: Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique. VLSI Design 2004: 901-906
20	EE	Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski: Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations. J. Electronic Testing 20(1): 11-23 (2004)
2003
19	EE	Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi: Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. DATE 2003: 10596-10601
18	EE	Petros Oikonomakos, Mark Zwolinski: Foundation of Combined Datapath and Controller Self-checking Design. IOLTS 2003: 30-34
17	EE	Andrew D. Brown, Mark Zwolinski: The continuous-discrete interface - What does this really mean? Modelling and simulation issues. ISCAS (3) 2003: 894-897
16		Duncan Crutchley, Mark Zwolinski: Globally convergent algorithms for DC operating point analysis of nonlinear circuits. IEEE Trans. Evolutionary Computation 7(1): 2-10 (2003)
15	EE	Mark Zwolinski, M. S. Gaur: Integrating testability with design space exploration. Microelectronics Reliability 43(5): 685-693 (2003)
2002
14	EE	Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç: Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS. DATE 2002: 1133
13	EE	Petros Oikonomakos, Mark Zwolinski: Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment. IOLTW 2002: 185
2001
12	EE	Yavuz Kiliç, Mark Zwolinski: Process variation independent built-in current sensor for analogue built-in self-test. ISCAS (4) 2001: 398-401
11	EE	Mark Zwolinski, R. W. Allen: Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits. ISCAS (5) 2001: 451-454
10	EE	Zheng Rong Yang, Mark Zwolinski: Mutual Information Theory for Adaptive Mixture Models. IEEE Trans. Pattern Anal. Mach. Intell. 23(4): 396-403 (2001)
9	EE	Mark Zwolinski: A technique for transparent fault injection and simulation in VHDL. Microelectronics Reliability 41(6): 797-804 (2001)
2000
8	EE	Zheng Rong Yang, Mark Zwolinski: Applying Mutual Information to Adaptive Mixture Models. IDEAL 2000: 250-255
7	EE	Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams: Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 142-151 (2000)
1999
6	EE	Zheng Rong Yang, Mark Zwolinski: Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits. DATE 1999: 244-248
1997
5	EE	Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski: Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. DFT 1997: 100-109
1992
4	EE	Andrew D. Brown, Mark Zwolinski, Ken G. Nichols, Tom J. Kazmierski: Confidence in mixed-mode circuit simulation. Computer-Aided Design 24(2): 115-118 (1992)
3	EE	Keith R. Baker, Mark Zwolinski: Interleaving: an additional topological compaction technique for Weinberger array generation. Computer-Aided Design 24(3): 169-176 (1992)
1991
2		Tom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski: A General Purpose Network Solving System. VLSI 1991: 147-156
1990
1	EE	Andrew D. Brown, Mark Zwolinski: Lee router modified for global routing. Computer-Aided Design 22(5): 296-300 (1990)

Coauthor Index

1	Arash Ahmadi	[30] [32]
2	Bashir M. Al-Hashimi	[19] [28]
3	Noohul Basheer Zain Ali	[28]
4	R. W. Allen	[11]
5	Karthik Baddam	[29] [33]
6	Keith R. Baker	[3]
7	Ian M. Bell	[5] [20]
8	Andrew D. Brown	[1] [2] [4] [14] [17] [22]
9	Chris D. Chalk	[5] [7] [20]
10	Duncan Crutchley	[16]
11	M. S. Gaur	[15] [21]
12	Peter Harrod	[28]
13	Tom J. Kazmierski	[2] [4]
14	Yavuz Kiliç	[12] [14]
15	Vanco B. Litovski	[23] [24]
16	Ken G. Nichols	[2] [4]
17	Petros Oikonomakos	[13] [18] [19] [25] [26]
18	J. Neil Ross	[14]
19	Xiaoxuan She	[31]
20	Stephen J. Spinks	[5] [20]
21	Miona Andrejevic Stosovic (Miona Andrejevic)	[23] [24]
22	Himanshu Thapliyal	[27]
23	Alan Christopher Williams	[7]
24	Peter R. Wilson	[14]
25	Zheng Rong Yang	[6] [7] [8] [10]

Colors in the list of coauthors