| 2007 |
|---|
| 57 | EE | Pankaj Golani,
Georgios D. Dimou,
Mallika Prakash,
Peter A. Beerel:
Design of a High-Speed Asynchronous Turbo Decoder.
ASYNC 2007: 49-59 |
| 2006 |
|---|
| 56 | EE | Sunan Tugsinavisut,
Roger Su,
Peter A. Beerel:
High-level Synthesis for Highly Concurrent Hardware Systems.
ACSD 2006: 79-90 |
| 55 | EE | Peter A. Beerel,
Nam-Hoon Kim,
Andrew Lines,
Mike Davies:
Slack Matching Asynchronous Designs.
ASYNC 2006: 184-194 |
| 54 | EE | Pankaj Golani,
Peter A. Beerel:
High-Performance Noise-Robust Asynchronous Circuits.
ISVLSI 2006: 173-178 |
| 53 | EE | Peter A. Beerel:
Asynchronous Design for High-Speed and Low-Power Circuits.
PATMOS 2006: 669 |
| 52 | EE | Recep O. Ozdag,
Peter A. Beerel:
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.
IEEE Trans. VLSI Syst. 14(9): 975-985 (2006) |
| 51 | EE | Sangyun Kim,
Peter A. Beerel:
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 389-402 (2006) |
| 50 | EE | Pankaj Golani,
Peter A. Beerel:
Back-Annotation in High-Speed Asynchronous Design.
J. Low Power Electronics 2(1): 37-44 (2006) |
| 2005 |
|---|
| 49 | | Arash Saifhashemi,
Peter A. Beerel:
High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog.
CPA 2005: 275-288 |
| 48 | EE | Pankaj Golani,
Peter A. Beerel:
Back Annotation in High Speed Asynchronous Design.
PATMOS 2005: 227-236 |
| 47 | EE | Sunan Tugsinavisut,
Youpyo Hong,
Daewook Kim,
Kyeounsoo Kim,
Peter A. Beerel:
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.
IEEE Trans. VLSI Syst. 13(4): 448-461 (2005) |
| 2004 |
|---|
| 46 | EE | Recep O. Ozdag,
Peter A. Beerel:
A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates.
ASYNC 2004: 187-197 |
| 45 | EE | Marcos Ferretti,
Recep O. Ozdag,
Peter A. Beerel:
High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.
ASYNC 2004: 95-105 |
| 44 | EE | Peter A. Beerel,
Jordi Cortadella,
Alex Kondratyev:
Bridging the Gap between Asynchronous Design and Designers.
VLSI Design 2004: 18-20 |
| 2003 |
|---|
| 43 | EE | Sunan Tugsinavisut,
Suwicha Jirayucharoensak,
Peter A. Beerel:
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.
ISCAS (5) 2003: 361-364 |
| 42 | EE | Joong-Seok Moon,
William C. Athas,
Sigfrid D. Soli,
Jeffrey T. Draper,
Peter A. Beerel:
Voltage-pulse driven harmonic resonant rail drivers for low-power applications.
IEEE Trans. VLSI Syst. 11(5): 762-777 (2003) |
| 2002 |
|---|
| 41 | EE | Peter A. Beerel,
Ken S. Stevens,
Hoshik Kim:
Relative Timing Based Verification of Timed Circuits and Systems.
ASYNC 2002: 115- |
| 40 | EE | Recep O. Ozdag,
Peter A. Beerel:
High-Speed QDI Asynchronous Pipelines.
ASYNC 2002: 13-22 |
| 39 | EE | Peter A. Beerel,
Aiguo Xie:
Performance Analysis of Asynchronous Circuits Using Markov Chains.
Concurrency and Hardware Design 2002: 313-344 |
| 38 | EE | Recep O. Ozdag,
Peter A. Beerel,
Montek Singh,
Steven M. Nowick:
High-Speed Non-Linear Asynchronous Pipelines.
DATE 2002: 1000-1007 |
| 37 | EE | Marcos Ferretti,
Peter A. Beerel:
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding.
DATE 2002: 1008-1015 |
| 36 | EE | Sunan Tugsinavisut,
Peter A. Beerel:
Control Circuit Templates for Asynchronous Bundled-Data Pipelines.
DATE 2002: 1098 |
| 35 | EE | Peter A. Beerel:
Asynchronous Circuits: An Increasingly Practical Design Solution (invited).
ISQED 2002: 367-372 |
| 34 | EE | Sangyun Kim,
Sunan Tugsinavisut,
Peter A. Beerel:
Reducing probabilistic timed petri nets for asynchronous architectural analysis.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 140-147 |
| 2001 |
|---|
| 33 | EE | Joong-Seok Moon,
William C. Athas,
Peter A. Beerel:
Theory and practical implementation of harmonic resonant rail driver.
ISLPED 2001: 153-158 |
| 2000 |
|---|
| 32 | | Sangyun Kim,
Peter A. Beerel:
Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm.
ICCAD 2000: 296-302 |
| 31 | EE | Kyeounsoo Kim,
Peter A. Beerel,
Youpyo Hong:
An asynchronous matrix-vector multiplier for discrete cosine transform.
ISLPED 2000: 256-261 |
| 30 | EE | Youpyo Hong,
Peter A. Beerel,
Jerry R. Burch,
Kenneth L. McMillan:
Sibling-substitution-based BDD minimization using don't cares.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 44-55 (2000) |
| 29 | EE | Aiguo Xie,
Peter A. Beerel:
Implicit enumeration of strongly connected components and anapplication to formal verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1225-1230 (2000) |
| 1999 |
|---|
| 28 | EE | Shai Rotem,
Ken S. Stevens,
Charles Dike,
Marly Roncken,
Boris Agapiev,
Ran Ginosar,
Rakefet Kol,
Peter A. Beerel,
Chris J. Myers,
Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder.
ASYNC 1999: 60-70 |
| 27 | EE | Aiguo Xie,
Sangyun Kim,
Peter A. Beerel:
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice.
ASYNC 1999: 94-107 |
| 26 | EE | Hüsnü Yenigün,
Vladimir Levin,
Doron Peled,
Peter A. Beerel:
Hazard-Freedom Checking in Speed-Independent Systems.
CHARME 1999: 317-320 |
| 25 | EE | Youpyo Hong,
Peter A. Beerel:
Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares.
DATE 1999: 13- |
| 24 | EE | Aiguo Xie,
Peter A. Beerel:
Implicit enumeration of strongly connected components.
ICCAD 1999: 37-40 |
| 23 | EE | Peter A. Beerel,
Sangyun Kim,
Pei-Chuan Yeh,
Kyeounsoo Kim:
Statistically optimized asynchronous barrel shifters for variable length codecs.
ISLPED 1999: 261-263 |
| 22 | EE | Wei-Chun Chou,
Peter A. Beerel,
Kenneth Y. Yun:
Average-case technology mapping of asynchronous burst-mode circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1418-1434 (1999) |
| 21 | EE | Aiguo Xie,
Peter A. Beerel:
Accelerating Markovian analysis of asynchronous systems using state compression.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 869-888 (1999) |
| 1998 |
|---|
| 20 | EE | Aiguo Xie,
Peter A. Beerel:
Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression.
ASYNC 1998: 247- |
| 19 | EE | Wei-Chun Chou,
Peter A. Beerel,
Ran Ginosar,
Rakefet Kol,
Chris J. Myers,
Shai Rotem,
Ken S. Stevens,
Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
ASYNC 1998: 80- |
| 18 | EE | Youpyo Hong,
Peter A. Beerel,
Luciano Lavagno,
Ellen Sentovich:
Don't Care-Based BDD Minimization for Embedded Software.
DAC 1998: 506-509 |
| 17 | EE | Aiguo Xie,
Peter A. Beerel:
Efficient State Classification of Finite State Markov Chains.
DAC 1998: 605-610 |
| 16 | | Peter A. Beerel,
Jerry R. Burch,
Teresa H. Y. Meng:
Checking Combinational Equivalence of Speed-Independent Circuits.
Formal Methods in System Design 13(1): 37-85 (1998) |
| 15 | EE | Kenneth Y. Yun,
Peter A. Beerel,
Vida Vakilotojar,
Ayoob E. Dooply,
Julio Arceo:
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver.
IEEE Trans. VLSI Syst. 6(4): 643-655 (1998) |
| 14 | EE | Aiguo Xie,
Peter A. Beerel:
Efficient state classification of finite-state Markov chains.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1334-1339 (1998) |
| 13 | EE | Peter A. Beerel,
Chris J. Myers,
Teresa H. Y. Meng:
Covering conditions and algorithms for the synthesis of speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 205-219 (1998) |
| 1997 |
|---|
| 12 | EE | Kenneth Y. Yun,
Ayoob E. Dooply,
Julio Arceo,
Peter A. Beerel,
Vida Vakilotojar:
The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver.
ASYNC 1997: 140- |
| 11 | EE | Steven M. Nowick,
Kenneth Y. Yun,
Ayoob E. Dooply,
Peter A. Beerel:
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.
ASYNC 1997: 210- |
| 10 | EE | Aiguo Xie,
Peter A. Beerel:
Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events.
ASYNC 1997: 64-75 |
| 9 | EE | Youpyo Hong,
Peter A. Beerel,
Jerry R. Burch,
Kenneth L. McMillan:
Safe BDD Minimization Using Don't Cares.
DAC 1997: 208-213 |
| 8 | EE | Vida Vakilotojar,
Peter A. Beerel:
RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking.
Integration 24(1): 19-35 (1997) |
| 1996 |
|---|
| 7 | EE | Peter A. Beerel,
Cheng-Ta Hsieh,
Suhrid A. Wadekar:
Estimation of energy consumption in speed-independent control circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 672-680 (1996) |
| 1995 |
|---|
| 6 | EE | Chris J. Myers,
Peter A. Beerel,
Teresa H. Y. Meng:
Technology mapping of timed circuits.
ASYNC 1995: 138- |
| 5 | EE | Peter A. Beerel,
Kenneth Y. Yun,
Steven M. Nowick,
Pei-Chuan Yeh:
Estimation and bounding of energy consumption in burst-mode control circuits.
ICCAD 1995: 26-33 |
| 4 | EE | Peter A. Beerel,
Cheng-Ta Hsieh,
Suhrid A. Wadekar:
Estimation of energy consumption in speed-independent control circuits.
ISLPD 1995: 39-44 |
| 1993 |
|---|
| 3 | EE | Peter A. Beerel,
Jerry R. Burch,
Teresa H. Y. Meng:
Efficient verification of determinate speed-independent circuits.
ICCAD 1993: 261-267 |
| 1992 |
|---|
| 2 | EE | Peter A. Beerel,
Teresa H. Y. Meng:
Automatic gate-level synthesis of speed-independent circuits.
ICCAD 1992: 581-586 |
| 1991 |
|---|
| 1 | EE | Peter A. Beerel,
Teresa H. Y. Meng:
Testability of Asynchronous Timed Control Circuits with Delay Assumptions.
DAC 1991: 446-451 |
