2008 |
30 | EE | Rehman Ashraf,
Malgorzata Chrzanowska-Jeske,
Siva G. Narendra:
Carbon nanotube circuit design choices in the presence of metallic tubes.
ISCAS 2008: 177-180 |
29 | EE | Grzegorz Blakiewicz,
Malgorzata Chrzanowska-Jeske:
Optimization of active circuits for substrate noise suppression.
ISCAS 2008: 3418-3421 |
2007 |
28 | EE | Tao Wan,
Malgorzata Chrzanowska-Jeske:
A novel net-degree distribution model and its application to floorplanning benchmark generation.
Integration 40(4): 420-433 (2007) |
2006 |
27 | EE | Jin S. Zhang,
Alan Mishchenko,
Robert K. Brayton,
Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.
DAC 2006: 510-515 |
26 | EE | Grzegorz Blakiewicz,
Malgorzata Chrzanowska-Jeske:
Estimation of supply current spectrum for early noise evaluation.
ISCAS 2006 |
25 | EE | Alan Mishchenko,
Jin S. Zhang,
Subarnarekha Sinha,
Jerry R. Burch,
Robert K. Brayton,
Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 743-755 (2006) |
24 | EE | Jin S. Zhang,
Malgorzata Chrzanowska-Jeske,
Alan Mishchenko,
Jerry R. Burch:
Linear cofactor relationships in Boolean functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1011-1023 (2006) |
2005 |
23 | EE | Jin S. Zhang,
Malgorzata Chrzanowska-Jeske,
Alan Mishchenko,
Jerry R. Burch:
Detecting support-reducing bound sets using two-cofactor symmetries.
ASP-DAC 2005: 266-271 |
22 | EE | Grzegorz Blakiewicz,
Marcin Jeske,
Malgorzata Chrzanowska-Jeske,
Jin S. Zhang:
Substrate noise modeling in early floorplanning of MS-SOCs.
ASP-DAC 2005: 819-823 |
21 | EE | Grzegorz Blakiewicz,
Malgorzata Chrzanowska-Jeske:
Modeling of substrate noise block properties for early prediction.
ISCAS (3) 2005: 3015-3018 |
20 | EE | Malgorzata Chrzanowska-Jeske,
Alan Mishchenko:
Synthesis for regularity using decision diagrams [logic IC synthesis and layout].
ISCAS (5) 2005: 4721-4724 |
2004 |
19 | | Marcin Jeske,
Grzegorz Blakiewicz,
Malgorzata Chrzanowska-Jeske,
Benyi Wang:
Substrate noise-aware floorplanning for mixed-signal SOCs.
ISCAS (2) 2004: 445-448 |
18 | | Tao Wan,
Malgorzata Chrzanowska-Jeske:
Generating random benchmark circuits for floorplanning.
ISCAS (5) 2004: 345-348 |
17 | EE | Tao Wan,
Malgorzata Chrzanowska-Jeske:
Prediction of interconnect net-degree distribution based on Rent's rule.
SLIP 2004: 107-114 |
2003 |
16 | EE | Yu Xia,
Malgorzata Chrzanowska-Jeske,
Benyi Wang,
Marcin Jeske:
Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.
ICCAD 2003: 100-106 |
15 | EE | Malgorzata Chrzanowska-Jeske,
Benyi Wang,
G. Greenwood:
Floorplanning with performance-based clustering.
ISCAS (4) 2003: 724-727 |
14 | EE | Niwat Waropus,
Rajendar Koltur,
Malgorzata Chrzanowska-Jeske:
Graph-based approach to evaluate net routability of a floorplan.
ISCAS (5) 2003: 465-468 |
13 | EE | Xiaoyu Song,
William N. N. Hung,
Alan Mishchenko,
Malgorzata Chrzanowska-Jeske,
Andrew A. Kennings,
Alan J. Coppola:
Board-level multiterminal net assignment for the partial cross-bar architecture.
IEEE Trans. VLSI Syst. 11(3): 511-514 (2003) |
12 | EE | Faran Rafiq,
Malgorzata Chrzanowska-Jeske,
Hannah Honghua Yang,
Marcin Jeske,
Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 730-741 (2003) |
2002 |
11 | EE | Xiaoyu Song,
William N. N. Hung,
Alan Mishchenko,
Malgorzata Chrzanowska-Jeske,
Alan J. Coppola,
Andrew A. Kennings:
Board-level multiterminal net assignment.
ACM Great Lakes Symposium on VLSI 2002: 130-135 |
10 | EE | Faran Rafiq,
Malgorzata Chrzanowska-Jeske,
Hannah Honghua Yang,
Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.
ISPD 2002: 56-61 |
2001 |
9 | EE | Marek A. Perkowski,
Malgorzata Chrzanowska-Jeske,
Alan Mishchenko,
Xiaoyu Song,
Anas Al-Rabadi,
Bart Massey,
Pawel Kerntopf,
Andrzej Buller,
Lech Józwiak,
Alan J. Coppola:
Regular Realization of Symmetric Functions Using Reversible Logic.
DSD 2001: 245-253 |
8 | EE | Wei Wang,
Malgorzata Chrzanowska-Jeske:
A global approach to the variable ordering problem in PSBDDs.
ISCAS (5) 2001: 117-120 |
1999 |
7 | EE | Malgorzata Chrzanowska-Jeske:
Regular symmetric arrays for non-symmetric functions.
ISCAS (1) 1999: 391-394 |
1995 |
6 | EE | Naveen Ramineni,
Malgorzata Chrzanowska-Jeske,
Naveen Buddi:
Tree restructuring approach to mapping problem in cellular-architecture FPGAs.
EURO-DAC 1995: 60-65 |
5 | EE | Naveen Buddi,
Malgorzata Chrzanowska-Jeske,
Charles L. Saxe:
Layout synthesis for datapath designs.
EURO-DAC 1995: 86-90 |
1994 |
4 | EE | Andisheh Sarabi,
Ning Song,
Malgorzata Chrzanowska-Jeske,
Marek A. Perkowski:
A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays.
DAC 1994: 321-326 |
3 | | Ning Song,
Malgorzata Chrzanowska-Jeske:
Output Column Folding for Cellular-Architecture FPGAs.
ISCAS 1994: 237-240 |
2 | | Marek A. Perkowski,
Malgorzata Chrzanowska-Jeske:
Multiple-Valued-Input TANT Networks.
ISMVL 1994: 334-341 |
1993 |
1 | | Malgorzata Chrzanowska-Jeske,
S. Goller,
I. Schafer:
An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD.
ISCAS 1993: 1782-1785 |