| 2009 |
|---|
| 169 | EE | Lei He,
Juan Li,
Qing Wang,
Ye Yang:
Predicting Upgrade Project Defects Based on Enhancement Requirements: An Empirical Study.
ICSP 2009: 268-279 |
| 168 | EE | Wei Yao,
Yiyu Shi,
Lei He,
Sudhakar Pamarti,
Yu Hu:
Worst case timing jitter and amplitude noise in differential signaling.
ISQED 2009: 40-46 |
| 167 | EE | Ju-Yueh Lee,
Yu Hu,
Rupak Majumdar,
Lei He:
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.
ISQED 2009: 702-707 |
| 166 | EE | Lerong Cheng,
Jinjun Xiong,
Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 130-140 (2009) |
| 165 | EE | Shenghua Liu,
Guoqiang Chen,
Tom Tong Jing,
Lei He,
Tianpei Zhang,
Robi Dutta,
Xian-Long Hong:
Substrate Topological Routing for High-Density Packages.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 207-216 (2009) |
| 164 | EE | Yu Hu,
Satyaki Das,
Steven Trimberger,
Lei He:
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 591-595 (2009) |
| 2008 |
|---|
| 163 | EE | Leronq Cheng,
Jinjun Xiong,
Lei He:
Non-Gaussian statistical timing analysis using second-order polynomial fitting.
ASP-DAC 2008: 298-303 |
| 162 | EE | Lei He,
Chunming Li,
Chenyang Xu:
Intensity statistics-based HSI diffusion for color photo denoising.
CVPR 2008 |
| 161 | EE | Zhen Cao,
Brian Foo,
Lei He,
Mihaela van der Schaar:
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications.
DAC 2008: 179-184 |
| 160 | EE | Yu Hu,
Victor Shih,
Rupak Majumdar,
Lei He:
FPGA area reduction by multi-output function based sequential resynthesis.
DAC 2008: 24-29 |
| 159 | EE | Shenghua Liu,
Guoqiang Chen,
Tom Tong Jing,
Lei He,
Tianpei Zhang,
Robi Dutta,
Xian-Long Hong:
Topological routing to maximize routability for package substrate.
DAC 2008: 566-569 |
| 158 | EE | Lerong Cheng,
Yan Lin,
Lei He:
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
FPGA 2008: 159-168 |
| 157 | EE | Lei He,
Xiangjie Ma,
Weili Zhang,
Yunfei Guo,
Wenbo Liu:
A Video Broadcast Architecture with Server Placement Programming.
GridNets 2008: 130-137 |
| 156 | EE | Lei He,
Xiangjie Ma,
Wenbo Liu,
Yunfei Guo:
A Peer-to-Peer Internet Video Broadcast System Utilizing the Locality Properties.
HPCC 2008: 404-411 |
| 155 | EE | Xiangjie Ma,
Lei He,
Xiaozhuo Gu,
Julong Lan,
Baisheng Zhang:
Study on a Novel Scheduling Algorithm ofthe Multiple-Plane and Multiple-Stage Switching Fabric.
HPCC 2008: 412-417 |
| 154 | EE | Yingjian Zhi,
Na Wang,
Binqiang Wang,
Lei He:
Urgency-Based Batching Policy for Streaming Media.
HPCC 2008: 580-585 |
| 153 | EE | Xiangjie Ma,
Xiaozhuo Gu,
Lei He,
Julong Lan,
Baisheng Zhang:
Performance Study on the MPMS Fabric: A Novel Parallel and Distributed Switching System Architecture.
HPCC 2008: 69-76 |
| 152 | EE | Yu Hu,
Zhe Feng,
Lei He,
Rupak Majumdar:
Robust FPGA resynthesis based on fault-tolerant Boolean matching.
ICCAD 2008: 706-713 |
| 151 | EE | Lei He,
Chenyang Xu:
Color Photo Denoising Via Hue, Saturation and Intensity Diffusion.
ICIAR 2008: 159-169 |
| 150 | EE | Lei He:
Spatially varying weighted HSI diffusion for color image denoising.
ICIP 2008: 581-584 |
| 149 | EE | Lei He,
Ashraf Saad,
Joy Reed,
Patrick Hannigan,
Edward Strauser:
Information technology education for k-12 students and teachers: from sensor network to comprehensive and customized web interaction.
SIGITE Conference 2008: 65-70 |
| 148 | EE | Ashraf Saad,
Lei He,
Joy Reed,
Edward Strauser,
Patrick Hannigan:
Ossabest: a comprehensive itest project for middle and high school teachers and students.
SIGITE Conference 2008: 71-76 |
| 147 | EE | Yu Hu,
Yan Lin,
Lei He,
Tim Tuan:
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 146 | EE | Hao Yu,
Yiyu Shi,
Lei He,
Tanay Karnik:
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.
IEEE Trans. VLSI Syst. 16(12): 1609-1619 (2008) |
| 145 | EE | Yan Lin,
Lei He,
Mike Hutton:
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.
IEEE Trans. VLSI Syst. 16(2): 124-133 (2008) |
| 144 | EE | Yu Hu,
Victor Shih,
Rupak Majumdar,
Lei He:
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1751-1760 (2008) |
| 143 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Zhe Feng,
Lei He,
Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008) |
| 142 | EE | Yiyu Shi,
Jinjun Xiong,
Chunchen Liu,
Lei He:
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1253-1263 (2008) |
| 141 | EE | King Ho Tam,
Yu Hu,
Lei He,
Tom Tong Jing,
Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1498-1502 (2008) |
| 140 | EE | Lei He,
Zhigang Peng,
Bryan Everding,
Xun Wang,
Chia Y. Han,
Kenneth L. Weiss,
William G. Wee:
A comparative study of deformable contour methods on medical image segmentation.
Image Vision Comput. 26(2): 141-163 (2008) |
| 2007 |
|---|
| 139 | EE | Lei He,
Patricia Brandt:
WEAS: a web-based educational assessment system.
ACM Southeast Regional Conference 2007: 126-131 |
| 138 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Lei He,
Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
ASP-DAC 2007: 256-261 |
| 137 | EE | Lerong Cheng,
Jinjun Xiong,
Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.
DAC 2007: 250-255 |
| 136 | EE | Hao Yu,
Chunta Chu,
Lei He:
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.
DAC 2007: 618-621 |
| 135 | EE | Yan Lin,
Lei He:
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.
DATE 2007: 636-641 |
| 134 | EE | Yan Lin,
Lei He:
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.
FPGA 2007: 80-88 |
| 133 | EE | Yu Hu,
Satyaki Das,
Steven Trimberger,
Lei He:
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.
ICCAD 2007: 188-193 |
| 132 | EE | Yan Lin,
Lei He:
Device and architecture concurrent optimization for FPGA transient soft error rate.
ICCAD 2007: 194-198 |
| 131 | EE | Yu Hu,
Victor Shih,
Rupak Majumdar,
Lei He:
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping.
ICCAD 2007: 350-353 |
| 130 | EE | Chunta Chu,
Xinyi Zhang,
Lei He,
Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load.
ICCAD 2007: 586-589 |
| 129 | EE | Yiyu Shi,
Jinjun Xiong,
Chunchen Liu,
Lei He:
Efficient decoupling capacitance budgeting considering operation and process variations.
ICCAD 2007: 803-810 |
| 128 | EE | Lei He,
Chuanjiang Luo,
Feng Zhu,
Yingming Hao,
Jinjun Ou,
Jing Zhou:
Depth Map Regeneration via Improved Graph Cuts Using a Novel Omnidirectional Stereo Sensor.
ICCV 2007: 1-8 |
| 127 | | Lei He,
Feng Zhu,
Yingming Hao:
A Comparative Study on Pose Estimation for Monocular Vision and Binocular Vision Without Modeling.
IPCV 2007: 627-631 |
| 126 | EE | Hao Yu,
Yu Hu,
Chunchen Liu,
Lei He:
Minimal skew clock embedding considering time variant temperature gradient.
ISPD 2007: 173-180 |
| 125 | EE | Yiyu Shi,
Lei He:
Empire: an efficient and compact multiple-parameterized model order reduction method.
ISPD 2007: 51-58 |
| 124 | EE | Lei He,
Chuanjiang Luo,
Yanfeng Geng,
Feng Zhu,
Yingming Hao:
Reliable Depth Map Regeneration Via a Novel Omnidirectional Stereo Sensor.
ISVC (1) 2007: 278-287 |
| 123 | EE | Yu Hu,
King Ho Tam,
Tong Jing,
Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling.
SLIP 2007: 95-102 |
| 122 | EE | Yiyu Shi,
Paul Mesa,
Hao Yu,
Lei He:
Circuit-simulated obstacle-aware Steiner routing.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 121 | EE | Changbo Long,
Lucanus J. Simonson,
Weiping Liao,
Lei He:
Microarchitecture Configurations and Floorplanning Co-Optimization.
IEEE Trans. VLSI Syst. 15(7): 830-841 (2007) |
| 120 | EE | Jinjun Xiong,
Vladimir Zolotov,
Lei He:
Robust Extraction of Spatial Correlation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 619-631 (2007) |
| 119 | EE | Jun Chen,
Lei He:
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 734-738 (2007) |
| 118 | EE | Jinjun Xiong,
Lei He:
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 739-742 (2007) |
| 117 | EE | Fei Li,
Yan Lin,
Lei He:
Field Programmability of Supply Voltages for FPGA Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 752-764 (2007) |
| 116 | EE | Lei He,
Andrew B. Kahng,
King Ho Tam,
Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 845-857 (2007) |
| 115 | EE | Lerong Cheng,
Fei Li,
Yan Lin,
Phoebe Wong,
Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1211-1221 (2007) |
| 114 | EE | Pu Liu,
Sheldon X.-D. Tan,
Bruce McGaughy,
Lifeng Wu,
Lei He:
TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1382-1392 (2007) |
| 113 | EE | Jinjun Xiong,
Lei He:
Full-chip multilevel routing for power and signal integrity.
Integration 40(3): 226-234 (2007) |
| 2006 |
|---|
| 112 | EE | Jinjun Xiong,
Yiu-Chung Wong,
Egino Sarto,
Lei He:
Constraint driven I/O planning and placement for chip-package co-design.
ASP-DAC 2006: 207-212 |
| 111 | EE | Yiyu Shi,
Tong Jing,
Lei He,
Zhe Feng,
Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.
ASP-DAC 2006: 630-635 |
| 110 | EE | Hao Yu,
Yiyu Shi,
Lei He:
Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
DAC 2006: 205-210 |
| 109 | EE | Yiyu Shi,
Paul Mesa,
Hao Yu,
Lei He:
Circuit simulation based obstacle-aware Steiner routing.
DAC 2006: 385-388 |
| 108 | EE | Yu Hu,
Yan Lin,
Lei He,
Tim Tuan:
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.
DAC 2006: 478-483 |
| 107 | EE | Lerong Cheng,
Jinjun Xiong,
Lei He,
Mike Hutton:
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.
FPL 2006: 1-6 |
| 106 | EE | Mike Hutton,
Yan Lin,
Lei He:
Placement and Timing for FPGAs Considering Variations.
FPL 2006: 1-7 |
| 105 | EE | Hao Yu,
Yiyu Shi,
Lei He,
David Smart:
A fast block structure preserving model order reduction for inverse inductance circuits.
ICCAD 2006: 7-12 |
| 104 | EE | Hao Yu,
Joanna Ho,
Lei He:
Simultaneous power and thermal integrity driven via stapling in 3D ICs.
ICCAD 2006: 802-808 |
| 103 | EE | Lei He,
Chia Y. Han,
William G. Wee:
Object Recognition and Recovery by Skeleton Graph Matching.
ICME 2006: 993-996 |
| 102 | EE | Hao Yu,
Yiyu Shi,
Lei He,
Tanay Karnik:
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.
ISLPED 2006: 156-161 |
| 101 | EE | Yan Lin,
Yu Hu,
Lei He,
Vijay Raghunat:
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.
ISLPED 2006: 168-173 |
| 100 | EE | Changbo Long,
Sasank Reddy,
Sudhakar Pamarti,
Lei He,
Tanay Karnik:
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.
ISLPED 2006: 326-329 |
| 99 | EE | Jinjun Xiong,
Lei He:
Fast buffer insertion considering process variations.
ISPD 2006: 128-135 |
| 98 | EE | Jinjun Xiong,
Vladimir Zolotov,
Lei He:
Robust extraction of spatial correlation.
ISPD 2006: 2-9 |
| 97 | EE | Yiyu Shi,
Hao Yu,
Lei He:
SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.
ISPD 2006: 25-32 |
| 96 | EE | Jun Chen,
Lei He:
Noise driven in-package decoupling capacitor optimization for power integrity.
ISPD 2006: 94-101 |
| 95 | EE | Pei Ding,
Lei He,
Xiang Yan,
Rui Zhao,
Jie Hao:
Robust Mandarin Speech Recognition for Car Navigation Interface.
PCM 2006: 302-309 |
| 94 | EE | Yan Lin,
Lei He:
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2023-2034 (2006) |
| 93 | EE | Zhenyu Qi,
Hao Yu,
Pu Liu,
Sheldon X.-D. Tan,
Lei He:
Wideband passive multiport model order reduction and realization of RLCM circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1496-1509 (2006) |
| 92 | EE | Jun Chen,
Lei He:
Modeling and synthesis of multiport transmission line for multichannel communication.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1664-1676 (2006) |
| 2005 |
|---|
| 91 | EE | Hao Yu,
Lei He,
Zhenyu Qi,
Sheldon X.-D. Tan:
A wideband hierarchical circuit reduction for massively coupled interconnects.
ASP-DAC 2005: 111-114 |
| 90 | EE | Tong Jing,
Ling Zhang,
Jinghong Liang,
Jingyu Xu,
Xianlong Hong,
Jinjun Xiong,
Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.
ASP-DAC 2005: 115-120 |
| 89 | EE | Zhenyu Qi,
Sheldon X.-D. Tan,
Hao Yu,
Lei He:
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
ASP-DAC 2005: 224-229 |
| 88 | EE | Yan Lin,
Fei Li,
Lei He:
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
ASP-DAC 2005: 645-650 |
| 87 | EE | Jinjun Xiong,
Lei He:
Probabilistic congestion model considering shielding for crosstalk reduction.
ASP-DAC 2005: 739-742 |
| 86 | EE | Bodo Rosenhahn,
Lei He,
Reinhard Klette:
Automatic Human Model Generation.
CAIP 2005: 41-48 |
| 85 | EE | King Ho Tam,
Lei He:
Power optimal dual-Vdd buffered tree considering buffer stations and blockages.
DAC 2005: 497-502 |
| 84 | EE | Yan Lin,
Lei He:
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.
DAC 2005: 720-725 |
| 83 | EE | Lerong Cheng,
Phoebe Wong,
Fei Li,
Yan Lin,
Lei He:
Device and architecture co-optimization for FPGA power reduction.
DAC 2005: 915-920 |
| 82 | EE | Jennifer L. Wong,
Weiping Liao,
Fei Li,
Lei He,
Miodrag Potkonjak:
Scheduling of Soft Real-Time Systems for Context-Aware Applications.
DATE 2005: 318-323 |
| 81 | EE | Jinjun Xiong,
King Ho Tam,
Lei He:
Buffer Insertion Considering Process Variation.
DATE 2005: 970-975 |
| 80 | EE | Yan Lin,
Fei Li,
Lei He:
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.
FPGA 2005: 199-207 |
| 79 | | Ho-Yan Wong,
Lerong Cheng,
Yan Lin,
Lei He:
FPGA device and architecture evaluation considering process variations.
ICCAD 2005: 19-24 |
| 78 | | Pu Liu,
Sheldon X.-D. Tan,
Hang Li,
Zhenyu Qi,
Jun Kong,
Bruce McGaughy,
Lei He:
An efficient method for terminal reduction of interconnect circuits considering delay variations.
ICCAD 2005: 821-826 |
| 77 | EE | Bin Chen,
Lei He,
Ping Liu:
A Morphological Edge Detector for Gray-Level Image Thresholding.
ICIAR 2005: 659-666 |
| 76 | EE | Hao Yu,
Lei He:
A sparsified vector potential equivalent circuit model for massively coupled interconnects.
ISCAS (1) 2005: 105-108 |
| 75 | EE | Yu Ching Chang,
King Ho Tam,
Lei He:
Power-optimal repeater insertion considering Vdd and Vth as design freedoms.
ISLPED 2005: 137-142 |
| 74 | EE | Lei He,
Mike Hutton,
Tim Tuan,
Steven J. E. Wilton:
Challenges and opportunities for low power FPGAs in nanometer technologies.
ISLPED 2005: 90 |
| 73 | EE | Lei He,
Andrew B. Kahng,
King Ho Tam,
Jinjun Xiong:
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
ISPD 2005: 78-85 |
| 72 | EE | Anirudh Devgan,
Luca Daniel,
Byron Krauter,
Lei He:
Modeling and Design of Chip-Package Interface.
ISQED 2005: 6 |
| 71 | EE | Hao Yu,
Lei He:
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.
ISQED 2005: 682-687 |
| 70 | EE | Lei Zhu,
Lei He,
Alex Collier:
MAPIS: A Mobile Amphibian Population Information System.
ITCC (2) 2005: 254-259 |
| 69 | EE | Lucanus J. Simonson,
Lei He:
Micro-architecture Performance Estimation by Formula.
SAMOS 2005: 192-201 |
| 68 | EE | Weiping Liao,
Joseph M. Basile,
Lei He:
Microarchitecture-level leakage reduction with data retention.
IEEE Trans. VLSI Syst. 13(11): 1324-1328 (2005) |
| 67 | EE | Jinjun Xiong,
Lei He:
Extended global routing with RLC crosstalk constraints.
IEEE Trans. VLSI Syst. 13(3): 319-329 (2005) |
| 66 | EE | Yan Lin,
Fei Li,
Lei He:
Circuits and architectures for field programmable gate array with configurable supply voltage.
IEEE Trans. VLSI Syst. 13(9): 1035-1047 (2005) |
| 65 | EE | Fei Li,
Yizhou Lin,
Lei He,
Deming Chen,
Jason Cong:
Power modeling and characteristics of field programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005) |
| 64 | EE | Jun Chen,
Lei He:
Piecewise linear model for transmission line with capacitive loading and ramp input.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 928-937 (2005) |
| 63 | EE | Weiping Liao,
Lei He,
Kevin M. Lepak:
Temperature and supply Voltage aware performance and power modeling at microarchitecture level.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1042-1053 (2005) |
| 62 | EE | Jun Chen,
Lei He:
Worst case crosstalk noise for nonswitching victims in high-speed buses.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1275-1283 (2005) |
| 61 | EE | Hao Yu,
Lei He:
A provably passive and cost-efficient model for inductive interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1283-1294 (2005) |
| 60 | EE | Weiping Liao,
Lei He:
Microarchitecture Level Interconnect Modeling Considering Layout Optimization.
J. Low Power Electronics 1(3): 297-308 (2005) |
| 2004 |
|---|
| 59 | EE | Jun Chen,
Lei He:
Modeling of coplanar waveguide for buffered clock tree.
ASP-DAC 2004: 367-372 |
| 58 | EE | Fei Li,
Lei He,
Joseph M. Basile,
Rakesh J. Patel,
Hema Ramamurthy:
High-level area and power-up current estimation considering rich cell library.
ASP-DAC 2004: 899-904 |
| 57 | EE | Lei He,
Weiping Liao,
Mircea R. Stan:
System level leakage reduction considering the interdependence of temperature and leakage.
DAC 2004: 12-17 |
| 56 | EE | Changbo Long,
Lucanus J. Simonson,
Weiping Liao,
Lei He:
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.
DAC 2004: 640-645 |
| 55 | EE | Fei Li,
Yan Lin,
Lei He:
FPGA power reduction using configurable dual-Vdd.
DAC 2004: 735-740 |
| 54 | EE | Jinjun Xiong,
Lei He:
Full-Chip Multilevel Routing for Power and Signal Integrity.
DATE 2004: 1116-1123 |
| 53 | EE | Deming Chen,
Jason Cong,
Fei Li,
Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages.
FPGA 2004: 109-117 |
| 52 | EE | Fei Li,
Yan Lin,
Lei He,
Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.
FPGA 2004: 42-50 |
| 51 | EE | Fei Li,
Yan Lin,
Lei He:
Vdd programmability to reduce FPGA interconnect power.
ICCAD 2004: 760-765 |
| 50 | EE | Lei He,
Tulika Mitra,
Weng-Fai Wong:
Configuration bitstream compression for dynamically reconfigurable FPGAs.
ICCAD 2004: 766-773 |
| 49 | | Xin Zhao,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Lei He,
Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk.
ISCAS (5) 2004: 297-300 |
| 48 | | Ling Zhang,
Tong Jing,
Xianlong Hong,
Jingyu Xu,
Jinjun Xiong,
Lei He:
Performance and RLC crosstalk driven global routing.
ISCAS (5) 2004: 65-68 |
| 47 | EE | Changbo Long,
Jinjun Xiong,
Lei He:
On optimal physical synthesis of sleep transistors.
ISPD 2004: 156-161 |
| 46 | EE | Lucanus J. Simonson,
King Ho Tam,
Nataraj Akkiraju,
Mosur Mohan,
Lei He:
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.
ISQED 2004: 69-74 |
| 45 | EE | Kevin M. Lepak,
Min Xu,
Jun Chen,
Lei He:
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.
ACM Trans. Design Autom. Electr. Syst. 9(3): 290-309 (2004) |
| 44 | EE | Changbo Long,
Lei He:
Distributed sleep transistor network for power reduction.
IEEE Trans. VLSI Syst. 12(9): 937-946 (2004) |
| 43 | EE | Jinjun Xiong,
Lei He:
Full-chip routing optimization with RLC crosstalk budgeting.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 366-377 (2004) |
| 42 | EE | Xun Wang,
Lei He,
William G. Wee:
Deformable Contour Method: A Constrained Optimization Approach.
International Journal of Computer Vision 59(1): 87-108 (2004) |
| 41 | EE | Lei He,
Chia Y. Han,
Bryan Everding,
William G. Wee:
Graph matching for object recognition and recovery.
Pattern Recognition 37(7): 1557-1560 (2004) |
| 2003 |
|---|
| 40 | EE | Changbo Long,
Lei He:
Distributed sleep transistor network for power reduction.
DAC 2003: 181-186 |
| 39 | EE | Hao Yu,
Lei He:
Vector potential equivalent circuit based on PEEC inversion.
DAC 2003: 718-723 |
| 38 | EE | Fei Li,
Deming Chen,
Lei He,
Jason Cong:
Architecture evaluation for power-efficient FPGAs.
FPGA 2003: 175-184 |
| 37 | EE | Weiping Liao,
Lei He:
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.
ICCAD 2003: 574-580 |
| 36 | EE | Weiping Liao,
Fei Li,
Lei He:
Microarchitecture level power and thermal simulation considering temperature dependent leakage model.
ISLPED 2003: 211-216 |
| 35 | EE | Weiping Liao,
Lei He:
Coupled Power and Thermal Simulation with Active Cooling.
PACS 2003: 148-163 |
| 34 | EE | Fei Li,
Lei He,
Joseph M. Basile,
Rakesh Patel,
Hema Ramamurthy:
High Level Area and Current Estimation.
PATMOS 2003: 259-268 |
| 33 | | Xun Wang,
Lei He,
Yingjie Tang,
William G. Wee:
A divide and conquer deformable contour method with a model based searching algorithm.
IEEE Transactions on Systems, Man, and Cybernetics, Part B 33(5): 738-751 (2003) |
| 2002 |
|---|
| 32 | EE | Jun Chen,
Lei He:
A decoupling method for analysis of coupled RLC interconnects.
ACM Great Lakes Symposium on VLSI 2002: 41-46 |
| 31 | EE | Xun Wang,
Lei He,
Chia Y. Han,
William G. Wee:
Deformable contour method: a constrained optimization approach.
BMVC 2002 |
| 30 | EE | James D. Z. Ma,
Lei He:
Towards global routing with RLC crosstalk constraints.
DAC 2002: 669-672 |
| 29 | EE | Jinjun Xiong,
Jun Chen,
James Ma,
Lei He:
Post global routing RLC crosstalk budgeting.
ICCAD 2002: 504-509 |
| 28 | EE | Weiping Liao,
Joseph M. Basile,
Lei He:
Leakage power modeling and reduction with data retention.
ICCAD 2002: 714-719 |
| 27 | | Xun Wang,
Lei He,
William G. Wee:
Constrained optimization: a geodesic snake approach.
ICIP (2) 2002: 77-80 |
| 26 | | Lei He,
Chia Y. Han,
Xun Wang,
Xiaokun Li,
William G. Wee:
A skeleton based shape matching and recovery approach.
ICIP (3) 2002: 789-792 |
| 25 | | Xiaokun Li,
Feng Gao,
Bryan Everding,
Lei He,
William G. Wee:
Error analysis, modeling, and correction for 3-D range data.
ICIP (3) 2002: 873-876 |
| 24 | EE | Jun Chen,
Lei He:
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 92-97 |
| 23 | EE | Fei Li,
Lei He,
Kewal K. Saluja:
Estimation of Maximum Power-Up Current.
VLSI Design 2002: 51- |
| 2001 |
|---|
| 22 | EE | Min Xu,
Lei He:
An efficient model for frequency-dependent on-chip inductance.
ACM Great Lakes Symposium on VLSI 2001: 115-120 |
| 21 | EE | Liang Yin,
Lei He:
An efficient analytical model of coupled on-chip RLC interconnects.
ASP-DAC 2001: 385-390 |
| 20 | EE | Kevin M. Lepak,
Irwan Luwandi,
Lei He:
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint.
DAC 2001: 199-202 |
| 19 | EE | James D. Z. Ma,
Lei He:
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering.
ICCAD 2001: 327-332 |
| 18 | | James D. Z. Ma,
Arvind Parihar,
Lei He:
Pre-routing Estimation of Shielding for RLC Signal Integrity.
ICCD 2001: 553-556 |
| 17 | EE | Fei Li,
Lei He:
Maximum current estimation considering power gating.
ISPD 2001: 106-111 |
| 16 | EE | Zhenyu Tang,
Lei He,
Norman Chang,
Shen Lin,
Weize Xie,
O. Sam Nakagawa:
Instruction Prediction for Step Power Reduction.
ISQED 2001: 211-216 |
| 15 | EE | James D. Z. Ma,
Lei He:
Simultaneous signal and power routing under K model.
SLIP 2001: 175-182 |
| 14 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001) |
| 2000 |
|---|
| 13 | | Yingjie Tang,
Lei He,
Xun Wang,
William G. Wee:
A Model Based Contour Searching Method.
BIBE 2000: 347-354 |
| 12 | EE | Norman Chang,
Shen Lin,
O. Sam Nakagawa,
Weize Xie,
Lei He:
Clocktree RLC Extraction with Efficient Inductance Modeling.
DATE 2000: 522- |
| 11 | EE | Lei He,
Kevin M. Lepak:
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.
ISPD 2000: 55-60 |
| 10 | EE | Zhenyu Tang,
Norman Chang,
Shen Lin,
Weize Xie,
O. Sam Nakagawa,
Lei He:
Ramp Up/Down Functional Unit to Reduce Step Power.
PACS 2000: 13-24 |
| 1999 |
|---|
| 9 | EE | Jason Cong,
Lei He:
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 406-420 (1999) |
| 1998 |
|---|
| 8 | EE | Jason Cong,
Lei He:
An efficient technique for device and interconnect optimization in deep submicron designs.
ISPD 1998: 45-51 |
| 1997 |
|---|
| 7 | EE | Jason Cong,
Lei He,
Andrew B. Kahng,
David Noice,
Nagesh Shirali,
Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.
DAC 1997: 627-632 |
| 6 | EE | Jason Cong,
David Zhigang Pan,
Lei He,
Cheng-Kok Koh,
Kei-Yong Khoo:
Interconnect design for deep submicron ICs.
ICCAD 1997: 478-485 |
| 5 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance.
ICCAD 1997: 628-633 |
| 1996 |
|---|
| 4 | EE | Jason Cong,
Lei He:
An efficient approach to simultaneous transistor and interconnect sizing.
ICCAD 1996: 181-186 |
| 3 | EE | Jason Cong,
Lei He:
Optimal wiresizing for interconnects with multiple sources.
ACM Trans. Design Autom. Electr. Syst. 1(4): 478-511 (1996) |
| 2 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
Patrick H. Madden:
Performance optimization of VLSI interconnect layout.
Integration 21(1-2): 1-94 (1996) |
| 1995 |
|---|
| 1 | EE | Jason Cong,
Lei He:
Optimal wiresizing for interconnects with multiple sources.
ICCAD 1995: 568-574 |
