| 2008 |
|---|
| 13 | EE | Ruiming Chen,
Lizheng Zhang,
Vladimir Zolotov,
Chandu Visweswariah,
Jinjun Xiong:
Static timing: Back to our roots.
ASP-DAC 2008: 310-315 |
| 12 | EE | Ruiming Chen,
Hai Zhou:
Fast Estimation of Timing Yield Bounds for Process Variations.
IEEE Trans. VLSI Syst. 16(3): 241-248 (2008) |
| 2007 |
|---|
| 11 | EE | Ruiming Chen,
Hai Zhou:
Fast Buffer Insertion for Yield Optimization Under Process Variations.
ASP-DAC 2007: 19-24 |
| 10 | EE | Ruiming Chen,
Hai Zhou:
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching.
ASP-DAC 2007: 462-467 |
| 9 | EE | Ruiming Chen,
Hai Zhou:
Fast Min-Cost Buffer Insertion under Process Variations.
DAC 2007: 338-343 |
| 8 | EE | Ruiming Chen,
Hai Zhou:
Timing budgeting under arbitrary process variations.
ICCAD 2007: 344-349 |
| 7 | EE | Ruiming Chen,
Hai Zhou:
An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2069-2073 (2007) |
| 2006 |
|---|
| 6 | EE | Ruiming Chen,
Hai Zhou:
An Efficient Data Structure for Maxplus Merge in Dynamic Programming.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3004-3009 (2006) |
| 5 | EE | Ruiming Chen,
Hai Zhou:
Statistical timing verification for transparently latched circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1847-1855 (2006) |
| 2005 |
|---|
| 4 | | Ruiming Chen,
Hai Zhou:
Efficient algorithms for buffer insertion in general circuits based on network flow.
ICCAD 2005: 322-326 |
| 2004 |
|---|
| 3 | EE | Ruiming Chen,
Hai Zhou:
Timing macro-modeling of IP blocks with crosstalk.
ICCAD 2004: 155-159 |
| 2 | EE | Ruiming Chen,
Hai Zhou:
Clock schedule verification under process variations.
ICCAD 2004: 619-625 |
| 1 | EE | Ruiming Chen,
Hai Zhou:
A Flexible Data Structure for Efficient Buffer Insertion.
ICCD 2004: 216-221 |
