| 2006 |
|---|
| 9 | EE | Miron Abramovici,
Paul Bradley,
Kumar N. Dwarakanath,
Peter Levin,
Gérard Memmi,
Dave Miller:
A reconfigurable design-for-debug infrastructure for SoCs.
DAC 2006: 7-12 |
| 8 | EE | Ronald D. Blanton,
Kumar N. Dwarakanath,
Rao Desineni:
Defect Modeling Using Fault Tuples.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2450-2464 (2006) |
| 2004 |
|---|
| 7 | EE | Chunsheng Liu,
Kumar N. Dwarakanath,
Krishnendu Chakrabarty,
Ronald D. Blanton:
Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.
ISVLSI 2004: 173-178 |
| 6 | EE | Sounil Biswas,
Kumar N. Dwarakanath,
R. D. (Shawn) Blanton:
Generalized Sensitization using Fault Tuples.
VTS 2004: 297-303 |
| 2003 |
|---|
| 5 | EE | R. D. (Shawn) Blanton,
Kumar N. Dwarakanath,
Anirudh B. Shah:
Analyzing the Effectiveness of Multiple-Detect Test Sets.
ITC 2003: 876-885 |
| 2002 |
|---|
| 4 | EE | Ronald D. Blanton,
John T. Chen,
Rao Desineni,
Kumar N. Dwarakanath,
Wojciech Maly,
Thomas J. Vogels:
Fault Tuples in Diagnosis of Deep-Submicron Circuits.
ITC 2002: 233-241 |
| 3 | EE | Kumar N. Dwarakanath,
R. D. (Shawn) Blanton:
Exploiting Dominance and Equivalence using Fault Tuples.
VTS 2002: 269-274 |
| 2000 |
|---|
| 2 | EE | Kumar N. Dwarakanath,
Ronald D. Blanton:
Universal fault simulation using fault tuples.
DAC 2000: 786-789 |
| 1 | | Rao Desineni,
Kumar N. Dwarakanath,
Ronald D. Blanton:
Universal test generation using fault tuples.
ITC 2000: 812-819 |
