2008 |
22 | EE | Esa Alghonaim,
Aiman El-Maleh,
Mohamed Adnan Landolsi:
Using input/output queues to increase LDPC decoder performance.
AICCSA 2008: 304-308 |
21 | EE | Aiman H. El-Maleh,
Bashir M. Al-Hashimi,
Aissa Melouki:
Transistor-level based defect tolerance for reliable nanoelectronics.
AICCSA 2008: 53-60 |
2006 |
20 | EE | Aiman El-Maleh:
An efficient test vector compression technique based on block merging.
ISCAS 2006 |
19 | EE | Aiman H. El-Maleh,
Sadiq M. Sait,
F. Nawaz Khan:
Finite state machine state assignment for area and power minimization.
ISCAS 2006 |
18 | EE | Aiman H. El-Maleh,
S. Saqib Khursheed,
Sadiq M. Sait:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2556-2564 (2006) |
2005 |
17 | EE | Aiman H. El-Maleh,
S. Saqib Khursheed,
Sadiq M. Sait:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation.
Asian Test Symposium 2005: 378-385 |
2004 |
16 | EE | Aiman H. El-Maleh,
Khaled Al-Utaibi:
An efficient test relaxation technique for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 933-940 (2004) |
2003 |
15 | EE | Sadiq M. Sait,
Aiman H. El-Maleh,
Rush H. Al-Abuji:
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning.
ISCAS (5) 2003: 457-460 |
14 | EE | Sadiq M. Sait,
Aiman H. El-Maleh,
Raslan H. Al-Abaji:
General iterative heuristics for VLSI multiobjective partitioning.
ISCAS (5) 2003: 497-500 |
13 | EE | Aiman H. El-Maleh,
Khaled Al-Utaibi:
On efficient extraction of partially specified test sets for synchronous sequential circuits.
ISCAS (5) 2003: 545-548 |
12 | EE | Aiman H. El-Maleh,
Khaled Al-Utaibi:
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits.
VTS 2003: 179-185 |
11 | EE | Aiman H. El-Maleh,
Yahya E. Osais:
Test vector decomposition-based static compaction algorithms for combinational circuits.
ACM Trans. Design Autom. Electr. Syst. 8(4): 430-459 (2003) |
2002 |
10 | EE | Aiman El-Maleh,
Ali Al-Suwaiyan:
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits.
VTS 2002: 53-59 |
2001 |
9 | | Sadiq M. Sait,
Habib Youssef,
Junaid A. Khan,
Aiman H. El-Maleh:
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement.
ICCD 2001: 484-487 |
8 | EE | Aiman H. El-Maleh,
Yahya E. Osais:
A retiming-based test pattern generator design for built-in self test of data path architectures.
ISCAS (4) 2001: 550-553 |
7 | EE | Aiman El-Maleh,
Esam Khan,
Saif al Zahir:
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip.
VTS 2001: 54-61 |
1998 |
6 | EE | Aiman H. El-Maleh,
Mark Kassab,
Janusz Rajski:
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.
DAC 1998: 625-631 |
1997 |
5 | EE | Aiman H. El-Maleh,
Thomas E. Marchok,
Janusz Rajski,
Wojciech Maly:
Behavior and testability preservation under the retiming transformation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 528-543 (1997) |
1996 |
4 | EE | Thomas E. Marchok,
Aiman H. El-Maleh,
Wojciech Maly,
Janusz Rajski:
A complexity analysis of sequential ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1409-1423 (1996) |
1995 |
3 | EE | Aiman H. El-Maleh,
Thomas E. Marchok,
Janusz Rajski,
Wojciech Maly:
On Test Set Preservation of Retimed Circuits.
DAC 1995: 176-182 |
2 | EE | Thomas E. Marchok,
Aiman H. El-Maleh,
Janusz Rajski,
Wojciech Maly:
Testability Implications of Performance-Driven Logic Synthesis.
IEEE Design & Test of Computers 12(2): 32-39 (1995) |
1 | EE | Aiman H. El-Maleh,
Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 582-590 (1995) |