| 2008 |
|---|
| 87 | EE | Anish Muttreja,
Srivaths Ravi,
Niraj K. Jha:
Variability-Tolerant Register-Transfer Level Synthesis.
VLSI Design 2008: 621-628 |
| 86 | EE | Rajesh Tiwari,
Abhijeet Shrivastava,
Mahit Warhadpande,
Srivaths Ravi,
Rubin A. Parekhji:
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.
VTS 2008: 53-58 |
| 85 | EE | Dimitris Gizopoulos,
Mihalis Psarakis,
Miltiadis Hatzimihail,
M. Maniatakos,
Antonis M. Paschalis,
Anand Raghunathan,
Srivaths Ravi:
Systematic Software-Based Self-Test for Pipelined Processors.
IEEE Trans. VLSI Syst. 16(11): 1441-1453 (2008) |
| 2007 |
|---|
| 84 | EE | Najwa Aaraj,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Energy and execution time analysis of a software-based trusted platform module.
DATE 2007: 1128-1133 |
| 83 | EE | Srivaths Ravi,
V. R. Devanathan,
Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic.
ICCAD 2007: 526-529 |
| 82 | EE | Srivaths Ravi,
Stefan Mangard:
Tutorial T1: Designing Secure SoCs.
VLSI Design 2007: 3 |
| 81 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Energy-optimizing source code transformations for operating system-driven embedded software.
ACM Trans. Embedded Comput. Syst. 7(1): (2007) |
| 80 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan:
Hardware Accelerated Power Estimation
CoRR abs/0710.4742: (2007) |
| 79 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.
IEEE Trans. VLSI Syst. 15(11): 1191-1204 (2007) |
| 78 | EE | Najwa Aaraj,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.
IEEE Trans. VLSI Syst. 15(3): 296-308 (2007) |
| 77 | EE | Nachiketh R. Potlapally,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha,
Ruby B. Lee:
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.
IEEE Trans. VLSI Syst. 15(4): 465-470 (2007) |
| 76 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties.
IEEE Trans. VLSI Syst. 15(5): 546-559 (2007) |
| 75 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Ruby B. Lee,
Niraj K. Jha:
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.
IEEE Trans. VLSI Syst. 15(5): 605-609 (2007) |
| 74 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. VLSI Syst. 15(6): 699-710 (2007) |
| 73 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Hybrid Simulation for Energy Estimation of Embedded Software.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1843-1854 (2007) |
| 72 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2035-2045 (2007) |
| 71 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Automated Energy/Performance Macromodeling of Embedded Software.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 542-552 (2007) |
| 2006 |
|---|
| 70 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Architectural support for safe software execution on embedded processors.
CODES+ISSS 2006: 106-111 |
| 69 | EE | Mihalis Psarakis,
Dimitris Gizopoulos,
Miltiadis Hatzimihail,
Antonis M. Paschalis,
Anand Raghunathan,
Srivaths Ravi:
Systematic software-based self-test for pipelined processors.
DAC 2006: 393-398 |
| 68 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
DAC 2006: 496-501 |
| 67 | EE | Najwa Aaraj,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Architectures for efficient face authentication in embedded systems.
DATE Designers' Forum 2006: 1-6 |
| 66 | EE | Nachiketh R. Potlapally,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha,
Ruby B. Lee:
Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
DATE Designers' Forum 2006: 18-23 |
| 65 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Active Learning Driven Data Acquisition for Sensor Networks.
ISCC 2006: 929-934 |
| 64 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Ruby B. Lee,
Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
VLSI Design 2006: 299-304 |
| 63 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.
VLSI Design 2006: 473-476 |
| 62 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.
IEEE Trans. Mob. Comput. 5(2): 128-143 (2006) |
| 61 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Scalable Synthesis Methodology for Application-Specific Processors.
IEEE Trans. VLSI Syst. 14(11): 1175-1188 (2006) |
| 60 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
IEEE Trans. VLSI Syst. 14(12): 1295-1308 (2006) |
| 59 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Use of Computation-Unit Integrated Memories in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1969-1989 (2006) |
| 58 | EE | Lin Zhong,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
RTL-Aware Cycle-Accurate Functional Power Estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2103-2117 (2006) |
| 57 | EE | Loganathan Lingappan,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha,
Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006) |
| 56 | EE | Loganathan Lingappan,
Srivaths Ravi,
Niraj K. Jha:
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 544-557 (2006) |
| 55 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Application-specific heterogeneous multiprocessor synthesis using extensible processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1589-1602 (2006) |
| 2005 |
|---|
| 54 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
SECA: security-enhanced communication architecture.
CASES 2005: 78-89 |
| 53 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties.
CODES+ISSS 2005: 190-195 |
| 52 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Hybrid simulation for embedded software energy estimation.
DAC 2005: 23-26 |
| 51 | EE | Pallav Gupta,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems.
DAC 2005: 244-247 |
| 50 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan:
Power emulation: a new paradigm for power estimation.
DAC 2005: 700-705 |
| 49 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.
DATE 2005: 178-183 |
| 48 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan:
Hardware Accelerated Power Estimation.
DATE 2005: 528-529 |
| 47 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.
VLSI Design 2005: 551-556 |
| 46 | EE | Loganathan Lingappan,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha,
Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.
VLSI Design 2005: 65-70 |
| 45 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Generation of distributed logic-memory architectures through high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1694-1711 (2005) |
| 2004 |
|---|
| 44 | EE | Srivaths Ravi,
Paul C. Kocher,
Ruby B. Lee,
Gary McGraw,
Anand Raghunathan:
Security as a new dimension in embedded system design.
DAC 2004: 753-760 |
| 43 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Automated energy/performance macromodeling of embedded software.
DAC 2004: 99-102 |
| 42 | EE | Lin Zhong,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Power estimation for cycle-accurate functional descriptions of hardware.
ICCAD 2004: 668-675 |
| 41 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
High-level synthesis using computation-unit integrated memories.
ICCAD 2004: 783-790 |
| 40 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.
VLSI Design 2004: 261-266 |
| 39 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Tamper Resistance Mechanisms for Secure, Embedded Systems.
VLSI Design 2004: 605- |
| 38 | EE | Srivaths Ravi,
Anand Raghunathan,
Paul C. Kocher,
Sunil Hattangady:
Security in embedded systems: Design challenges.
ACM Trans. Embedded Comput. Syst. 3(3): 461-491 (2004) |
| 37 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Custom-instruction synthesis for extensible-processor platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 216-228 (2004) |
| 36 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A hybrid energy-estimation technique for extensible processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 652-664 (2004) |
| 2003 |
|---|
| 35 | EE | Indradeep Ghosh,
Srivaths Ravi:
On automatic generation of RTL validation test benches using circuit testing techniques.
ACM Great Lakes Symposium on VLSI 2003: 289-294 |
| 34 | EE | Li Chen,
Srivaths Ravi,
Anand Raghunathan,
Sujit Dey:
A scalable software-based self-test methodology for programmable processors.
DAC 2003: 548-553 |
| 33 | EE | Anand Raghunathan,
Srivaths Ravi,
Sunil Hattangady,
Jean-Jacques Quisquater:
Securing Mobile Appliances: New Challenges for the System Designer.
DATE 2003: 10176-10183 |
| 32 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Energy Estimation for Extensible Processors.
DATE 2003: 10682-10687 |
| 31 | EE | Davide Bertozzi,
Anand Raghunathan,
Luca Benini,
Srivaths Ravi:
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
DATE 2003: 10706-10713 |
| 30 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Scalable Application-Specific Processor Synthesis Methodology.
ICCAD 2003: 283-290 |
| 29 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.
ICCAD 2003: 46-53 |
| 28 | EE | Loganathan Lingappan,
Srivaths Ravi,
Niraj K. Jha:
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.
ICCD 2003: 187-193 |
| 27 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Analyzing the energy consumption of security protocols.
ISLPED 2003: 30-35 |
| 26 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems.
VLSI Design 2003: 269-270 |
| 25 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs.
VLSI Design 2003: 431-439 |
| 2002 |
|---|
| 24 | EE | Srivaths Ravi,
Anand Raghunathan,
Nachiketh R. Potlapally,
Murugan Sankaradass:
System design methodologies for a wireless security processing platform.
DAC 2002: 777-782 |
| 23 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
High-level synthesis of distributed logic-memory architectures.
ICCAD 2002: 564-571 |
| 22 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Synthesis of custom processors based on extensible platforms.
ICCAD 2002: 641-648 |
| 21 | EE | Hiroto Yasuura,
Naofumi Takagi,
Srivaths Ravi,
Michael Torla,
Catherine H. Gebotys:
Special Session: Security on SoC.
ISSS 2002: 192-194 |
| 20 | EE | Anand Raghunathan,
Nachiketh R. Potlapally,
Srivaths Ravi:
Securing Wireless Data: System Architecture Challenges.
ISSS 2002: 195-200 |
| 19 | EE | Srivaths Ravi,
Niraj K. Jha:
Test synthesis of systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1211-1217 (2002) |
| 18 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
High-level test compaction techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 827-841 (2002) |
| 2001 |
|---|
| 17 | EE | Vijay Raghunathan,
Srivaths Ravi,
Anand Raghunathan,
Ganesh Lakshminarayana:
Transient Power Management Through High Level Synthesis.
ICCAD 2001: 545-552 |
| 16 | | Srivaths Ravi,
Niraj K. Jha:
Fast test generation for circuits with RTL and gate-level views.
ITC 2001: 1068-1077 |
| 15 | EE | Srivaths Ravi,
Niraj K. Jha:
Synthesis of System-on-a-chip for Testability.
VLSI Design 2001: 149-156 |
| 14 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
TAO: regular expression-based register-transfer level testability analysis and optimization.
IEEE Trans. VLSI Syst. 9(6): 824-832 (2001) |
| 13 | EE | Srivaths Ravi,
Indradeep Ghosh,
Vamsi Boppana,
Niraj K. Jha:
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1414-1425 (2001) |
| 12 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
Testing of core-based systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 426-439 (2001) |
| 2000 |
|---|
| 11 | EE | Srivaths Ravi,
Niraj K. Jha,
Indradeep Ghosh,
Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences.
ICCD 2000: 591- |
| 10 | | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
: Reducing test application time in high-level test generation.
ITC 2000: 829-838 |
| 9 | EE | Vijay Raghunathan,
Srivaths Ravi,
Ganesh Lakshminarayana:
High-Level Synthesis with Variable-Latency Components.
VLSI Design 2000: 220-227 |
| 8 | EE | Vijay Raghunathan,
Srivaths Ravi,
Ganesh Lakshminarayana:
Integrating variable-latency components into high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1105-1117 (2000) |
| 7 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 894-906 (2000) |
| 1999 |
|---|
| 6 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
A framework for testing core-based systems-on-a-chip.
ICCAD 1999: 385-390 |
| 5 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.
VTS 1999: 398-406 |
| 1998 |
|---|
| 4 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.
ICCAD 1998: 577-584 |
| 3 | EE | Srivaths Ravi,
Ganesh Lakshminarayana,
Niraj K. Jha:
TAO: regular expression based high-level testability analysis and optimization.
ITC 1998: 331-340 |
| 2 | EE | Srivaths Ravi,
Indradeep Ghosh,
Rabindra K. Roy,
Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.
VLSI Design 1998: 193-198 |
| 1 | EE | Srivaths Ravi,
Indradeep Ghosh,
Rabindra K. Roy,
Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.
J. Electronic Testing 13(2): 201-212 (1998) |
