| 2007 |
|---|
| 6 | EE | Srinath R. Naidu:
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits.
VLSI Design 2007: 265-270 |
| 2006 |
|---|
| 5 | EE | Jochen A. G. Jess,
K. Kalafala,
Srinath R. Naidu,
Ralph H. J. M. Otten,
Chandramouli Visweswariah:
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2376-2392 (2006) |
| 2003 |
|---|
| 4 | EE | Jochen A. G. Jess,
K. Kalafala,
Srinath R. Naidu,
Ralph H. J. M. Otten,
Chandramouli Visweswariah:
Statistical timing for parametric yield prediction of digital integrated circuits.
DAC 2003: 932-937 |
| 3 | EE | Srinath R. Naidu,
Vijay Chandru:
On Synthesis of Easily Testable (k, K) Circuits.
IEEE Trans. Computers 52(11): 1490-1494 (2003) |
| 2002 |
|---|
| 2 | EE | Srinath R. Naidu:
Timing Yield Calculation Using an Impulse-Train Approach.
VLSI Design 2002: 219-224 |
| 2001 |
|---|
| 1 | EE | Srinath R. Naidu,
E. T. A. F. Jacobs:
Minimizing stand-by leakage power in static CMOS circuits.
DATE 2001: 370-376 |
