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D. Bhatia

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2006
4EEP. Kannan, D. Bhatia: Interconnect estimation for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1523-1534 (2006)
2005
3EER. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia: Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design 2005: 451-456
2003
2EED. Bhatia, A. Sharma: New-invexity type conditions with applications to constrained dynamic games. European Journal of Operational Research 148(1): 48-55 (2003)
1990
1EED. Bhatia: Restructuring wafers for maximum yield and some applications of WSI. SPDP 1990: 750-753

Coauthor Index

1V. Kamakoti [3]
2P. Kannan [4]
3R. Manimegalai [3]
4V. Muralidharan [3]
5Balaraman Ravindran [3]
6A. Sharma [2]
7E. Siva Soumya [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)