Hua Xiang

2008
30	EE	Laura Grigori, James Demmel, Hua Xiang: Communication avoiding Gaussian elimination. SC 2008: 29
29	EE	Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008)
28	EE	Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008)
27	EE	Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: Track Routing and Optimization for Yield. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 872-882 (2008)
26	EE	Wenhua Kang, Hua Xiang: Level-2 condition numbers for least-squares solution of Kronecker product linear systems. Int. J. Comput. Math. 85(5): 827-841 (2008)
2007
25	EE	Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang: Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18
24	EE	Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58
23	EE	Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26
22	EE	Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10
21	EE	Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong: OPC-Friendly Bus Driven Floorplanning. ISQED 2007: 847-852
20	EE	Peilin Jiang, Hua Xiang, Fuji Ren, Shingo Kuroiwa, Nanning Zheng: The Framework of Mental State Transition Analysis. MICAI 2007: 1046-1055
19	EE	Haiming Zhang, Hua Xiang, Yimin Wei: Condition numbers for linear systems and Kronecker product linear systems with multiple right-hand sides. Int. J. Comput. Math. 84(12): 1805-1817 (2007)
2006
18	EE	Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri: Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492
17	EE	Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong: An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1754-1762 (2006)
2005
16	EE	Peilin Jiang, Hua Xiang, Fuji Ren, Shingo Kuroiwa: An Advanced Mental State Transition Network and Psychological Experiments. EUC 2005: 1026-1035
15	EE	Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong: Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186
14	EE	Hua Xiang, I-Min Liu, Martin D. F. Wong: Wire Planning with Bounded Over-the-Block Wires. ISQED 2005: 622-627
13	EE	Hua Xiang, Xiaoping Tang, Martin D. F. Wong: An algorithm for integrated pin assignment and buffer planning. ACM Trans. Design Autom. Electr. Syst. 10(3): 561-572 (2005)
12	EE	Yimin Wei, Yanhua Cao, Hua Xiang: A note on the componentwise perturbation bounds of matrix inverse and linear systems. Applied Mathematics and Computation 169(2): 1221-1236 (2005)
2004
11	EE	Hua Xiang, Kai-Yuan Chao, D. F. Wong: An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46
10	EE	Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu: A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 141-147 (2004)
9	EE	Hua Xiang, Xiaoping Tang, Martin D. F. Wong: Bus-driven floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1522-1530 (2004)
2003
8	EE	Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun: Wire type assignment for FPGA routing. FPGA 2003: 61-67
7	EE	Hua Xiang, Xiaoping Tang, Martin D. F. Wong: Bus-Driven Floorplanning. ICCAD 2003: 66-73
6	EE	Hua Xiang, Xiaoping Tang, Martin D. F. Wong: Min-cost flow-based algorithm for simultaneous pin assignment and routing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 870-878 (2003)
2002
5	EE	Hua Xiang, D. F. Wong, Xiaoping Tang: An algorithm for integrated pin assignment and buffer planning. DAC 2002: 584-589
4	EE	Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-477
3	EE	Hua Xiang, Kai-Yuan Chao, D. F. Wong: ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74
2001
2	EE	Hua Xiang, Xiaoping Tang, D. F. Wong: An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD 2001: 232-
1	EE	Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong: A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD 2001: 49-56

Coauthor Index

1	Yanhua Cao	[12]
2	Kai-Yuan Chao	[3] [11] [15] [17] [22] [23] [25] [28] [29]
3	Minsik Cho	[18] [24] [27]
4	James Demmel	[30]
5	Liang Deng	[21] [22] [25] [28]
6	Laura Grigori	[30]
7	Li-Da Huang	[4] [10] [21]
8	Peilin Jiang	[16] [20]
9	Wenhua Kang	[26]
10	Shingo Kuroiwa	[16] [20]
11	Seokjin Lee	[8]
12	I-Min Liu	[4] [10] [14]
13	David Z. Pan (David Zhigang Pan)	[18] [24] [27]
14	Ruchir Puri	[18] [22] [23] [24] [27] [28] [29]
15	Fuji Ren	[16] [20]
16	Richard Y. Sun	[8]
17	Xiaoping Tang	[1] [2] [4] [5] [6] [7] [9] [10] [13]
18	Ruiqi Tian	[1]
19	Yimin Wei	[12] [19]
20	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [17] [21] [22] [23] [25] [28] [29]
21	Haiming Zhang	[19]
22	Nanning Zheng	[20]

Colors in the list of coauthors