Philip Brisk

2009
25	EE	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286
24	EE	Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne: MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197
2008
23	EE	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143
22	EE	Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339
21	EE	Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216
20	EE	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248
19	EE	Ajay K. Verma, Philip Brisk, Paolo Ienne: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255
18	EE	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261
17	EE	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180
16	EE	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190
15	EE	Ajay K. Verma, Philip Brisk, Paolo Ienne: Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008)
2007
14	EE	Ajay K. Verma, Philip Brisk, Paolo Ienne: Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134
13	EE	Philip Brisk, Ajay K. Verma, Paolo Ienne: An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217
12	EE	Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar: Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337
11	EE	Ajay K. Verma, Philip Brisk, Paolo Ienne: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409
10	EE	Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179
9	EE	Philip Brisk, Majid Sarrafzadeh: Interference graphs for procedures in static single information form are interval graphs. SCOPES 2007: 101-110
2006
8	EE	Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh: Layout driven data communication optimization for high level synthesis. DATE 2006: 1185-1190
7	EE	Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh: Optimal register sharing for high-level synthesis of SSA form programs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 772-779 (2006)
2005
6	EE	Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh: A dictionary construction technique for code compression systems with echo instructions. LCTES 2005: 105-114
5	EE	Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh: Adaptive and fault tolerant medical vest for life-critical medical monitoring. SAC 2005: 272-279
2004
4	EE	Philip Brisk, Adam Kaplan, Majid Sarrafzadeh: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. DAC 2004: 395-400
3	EE	Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh: Instruction Selection for Compilers that Target Architectures with Echo Instructions. SCOPES 2004: 229-243
2003
2	EE	Adam Kaplan, Philip Brisk, Ryan Kastner: Data communication estimation and reduction for reconfigurable systems. DAC 2003: 616-621
2002
1	EE	Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh: Instruction generation and regularity extraction for reconfigurable processors. CASES 2002: 262-269

Coauthor Index

1	Panagiotis Athanasopoulos	[16] [25]
2	Forrest Brewer	[8]
3	Alessandro Cevrero	[16] [21] [25]
4	Edoardo Charbon	[20] [24]
5	Foad Dabiri	[5] [7]
6	Wenrui Gong	[8]
7	Frank K. Gürkaynak	[16] [21]
8	Xin Hao	[8]
9	Paolo Ienne	[10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]
10	Roozbeh Jafari	[5] [7]
11	Adam Kaplan	[1] [2] [4] [8]
12	Ryan Kastner	[1] [2] [8]
13	Theo Kluter	[20] [24]
14	Yusuf Leblebici	[16] [21] [25]
15	Jamie Macbeth	[6]
16	Ani Nahapetian	[3] [6]
17	Seyed Hosein Attarzadeh Niaki	[21]
18	Chrysostomos Nicopoulos	[21]
19	Hadi Parandeh-Afshar	[12] [16] [17] [18] [23] [25]
20	Majid Sarrafzadeh	[1] [3] [4] [5] [6] [7] [8] [9]
21	Maurizio Skerlj	[25]
22	Ajay K. Verma	[10] [11] [12] [13] [14] [15] [16] [19] [22]

Colors in the list of coauthors