John Lillis

2008
32	EE	Hosung (Leo) Kim, John Lillis: A framework for layout-level logic restructuring. ISPD 2008: 87-94
31	EE	Hosung Kim, John Lillis: A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2120-2132 (2008)
2007
30	EE	Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis: Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. ASP-DAC 2007: 609-615
29	EE	Salim Chowdhury, John Lillis: Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. ISPD 2007: 59-66
28	EE	Devang Jariwala, John Lillis: RBI: Simultaneous Placement and Routing Optimization Technique. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 127-141 (2007)
2006
27	EE	Hosung (Leo) Kim, John Lillis, Milos Hrkic: Techniques for improved placement-coupled logic replication. ACM Great Lakes Symposium on VLSI 2006: 211-216
26	EE	Devang Jariwala, John Lillis: Trunk decomposition based global routing optimization. ICCAD 2006: 472-479
25	EE	Milos Hrkic, John Lillis, Giancarlo Beraudo: An Approach to Placement-Coupled Logic Replication. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2539-2551 (2006)
2005
24	EE	Qingzhou (Ben) Wang, Devang Jariwala, John Lillis: A study of tighter lower bounds in LP relaxation based placement. ACM Great Lakes Symposium on VLSI 2005: 498-502
23	EE	Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal: An LP-based methodology for improved timing-driven placement. ASP-DAC 2005: 1139-1143
2004
22	EE	Milos Hrkic, John Lillis, Giancarlo Beraudo: An approach to placement-coupled logic replication. DAC 2004: 711-716
21	EE	Devang Jariwala, John Lillis: On interactions between routing and detailed placement. ICCAD 2004: 387-393
2003
20	EE	Giancarlo Beraudo, John Lillis: Timing optimization of FPGA placements by logic replication. DAC 2003: 196-201
19	EE	Milos Hrkic, John Lillis: Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 481-491 (2003)
2002
18		David P. LaPotin, Charles J. Alpert, John Lillis: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002 ACM 2002
17	EE	Milos Hrkic, John Lillis: S-Tree: a technique for buffered routing tree synthesis. DAC 2002: 578-583
16	EE	Milos Hrkic, John Lillis: Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. ISPD 2002: 98-103
15	EE	Ashok Jagannathan, Sung-Woo Hur, John Lillis: A fast algorithm for context-aware buffer insertion. ACM Trans. Design Autom. Electr. Syst. 7(1): 173-188 (2002)
2001
14	EE	Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9
2000
13	EE	Ashok Jagannathan, Sung-Woo Hur, John Lillis: A fast algorithm for context-aware buffer insertion. DAC 2000: 368-373
12		Sung-Woo Hur, John Lillis: MONGREL: Hybrid Techniques for Standard Cell Placement. ICCAD 2000: 165-170
11	EE	Sung-Woo Hur, Ashok Jagannathan, John Lillis: Timing-driven maze routing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 234-241 (2000)
1999
10	EE	Sung-Woo Hur, John Lillis: Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. DAC 1999: 360-366
9	EE	Sung-Woo Hur, Ashok Jagannathan, John Lillis: Timing driven maze routing. ISPD 1999: 208-213
8	EE	John Lillis, Chung-Kuan Cheng: Timing optimization for multisource nets: characterization andoptimal repeater insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 322-331 (1999)
1998
7	EE	John Lillis, Premal Buch: Table-Lookup Methods for Improved Performance-Driven Routing. DAC 1998: 368-373
1997
6	EE	John Lillis, Chung-Kuan Cheng: Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. DAC 1997: 214-219
1996
5	EE	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho: New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC 1996: 395-400
4	EE	Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng: New Spectral Linear Placement and Clustering Approach. DAC 1996: 88-93
3	EE	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153
1995
2	EE	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD 1995: 138-143
1	EE	Jianmin Li, John Lillis, Chung-Kuan Cheng: Linear decomposition algorithm for VLSI design applications. ICCAD 1995: 223-228

Coauthor Index

1	Charles J. Alpert	[14] [18]
2	Giancarlo Beraudo	[20] [22] [25]
3	Premal Buch	[7]
4	Chung-Kuan Cheng	[1] [2] [3] [4] [5] [6] [8] [30]
5	Salim Chowdhury	[29]
6	Chin-Yen Ho	[5]
7	Milos Hrkic	[14] [16] [17] [19] [22] [25] [27]
8	Jiang Hu	[14]
9	Sung-Woo Hur	[9] [10] [11] [12] [13] [15]
10	Ashok Jagannathan	[9] [11] [13] [15]
11	Devang Jariwala	[21] [24] [26] [28]
12	Andrew B. Kahng	[14]
13	Hosung Kim	[31]
14	Hosung (Leo) Kim	[27] [32]
15	David P. LaPotin	[18]
16	Jianmin Li	[1] [4]
17	Ting-Ting Y. Lin	[2] [3] [5]
18	Bao Liu	[14]
19	Jianhua Liu	[30]
20	Lung-Tien Liu	[4]
21	Stephen T. Quay	[14]
22	Shubhankar Sanyal	[23]
23	Sachin S. Sapatnekar	[14]
24	A. J. Sullivan	[14]
25	Paul G. Villarrubia (Paul Villarrubia)	[14]
26	Qingzhou (Ben) Wang	[23] [24]
27	Haikun Zhu	[30]
28	Yi Zhu	[30]

Colors in the list of coauthors