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Mahilchi Milir Vaseekar Kumar

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2007
7EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas: High-Quality Transition Fault ATPG for Small Delay Defects. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 983-989 (2007)
2006
6EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006)
2005
5EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas: Low power test generation for path delay faults using stability functions. ACM Great Lakes Symposium on VLSI 2005: 8-12
4EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Implicit and Exact Path Delay Fault Grading in Sequential Circuits. DATE 2005: 990-995
3EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas: Quality Transition Fault Tests Suitable for Small Delay Defects. ICCD 2005: 468-470
2EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas: Low Power Test Generation for Path Delay Faults. J. Low Power Electronics 1(2): 194-205 (2005)
2004
1EEMahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas: Low power ATPG for path delay faults. ACM Great Lakes Symposium on VLSI 2004: 389-392

Coauthor Index

1Sreejit Chakravarty [4] [6]
2Rathish Jayabharathi [4] [6]
3Saravanan Padmanaban [1]
4Spyros Tragoudas [1] [2] [3] [4] [5] [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)