| 2007 |
|---|
| 7 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
High-Quality Transition Fault ATPG for Small Delay Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 983-989 (2007) |
| 2006 |
|---|
| 6 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006) |
| 2005 |
|---|
| 5 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
Low power test generation for path delay faults using stability functions.
ACM Great Lakes Symposium on VLSI 2005: 8-12 |
| 4 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
DATE 2005: 990-995 |
| 3 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
Quality Transition Fault Tests Suitable for Small Delay Defects.
ICCD 2005: 468-470 |
| 2 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
Low Power Test Generation for Path Delay Faults.
J. Low Power Electronics 1(2): 194-205 (2005) |
| 2004 |
|---|
| 1 | EE | Mahilchi Milir Vaseekar Kumar,
Saravanan Padmanaban,
Spyros Tragoudas:
Low power ATPG for path delay faults.
ACM Great Lakes Symposium on VLSI 2004: 389-392 |
