2007 |
18 | EE | Steven M. Burns,
Mahesh Ketkar,
Noel Menezes,
Keith A. Bowman,
James Tschanz,
Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques.
DAC 2007: 238-243 |
17 | EE | Ming Zhang,
T. M. Mak,
James Tschanz,
Kee Sup Kim,
Norbert Seifert,
Davia Lu:
Design for Resilience to Soft Errors and Variations.
IOLTS 2007: 23-28 |
16 | EE | Gerhard Knoblinger,
James Tschanz,
Marcal Pol:
SUB-45nm Technology and Design Challenges.
ISQED 2007: 3 |
15 | EE | James Tschanz:
SUB 45nm Low Power Design Challenges.
ISQED 2007: 4 |
2006 |
14 | EE | Keith A. Bowman,
James Tschanz,
Muhammad M. Khellah,
Maged Ghoneima,
Yehea I. Ismail,
Vivek De:
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.
ISLPED 2006: 79-84 |
13 | EE | James Tschanz:
Session Abstract.
VTS 2006: 378-379 |
12 | EE | Osman S. Unsal,
James Tschanz,
Keith A. Bowman,
Vivek De,
Xavier Vera,
Antonio González,
Oguz Ergin:
Impact of Parameter Variations on Circuits and Microarchitecture.
IEEE Micro 26(6): 30-39 (2006) |
11 | EE | Maged Ghoneima,
Yehea I. Ismail,
Muhammad M. Khellah,
James Tschanz,
Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 821-836 (2006) |
2005 |
10 | EE | James Tschanz,
Keith A. Bowman,
Vivek De:
Variation-tolerant circuits: circuit solutions and techniques.
DAC 2005: 762-763 |
9 | | Maged Ghoneima,
Yehea I. Ismail,
Muhammad M. Khellah,
James Tschanz,
Vivek De:
Serial-link bus: a low-power on-chip bus architecture.
ICCAD 2005: 541-546 |
8 | EE | Muhammad M. Khellah,
Maged Ghoneima,
James Tschanz,
Yibin Ye,
Nasser Kurd,
Javed Barkatullah,
Srikanth Nimmagadda,
Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.
ICCD 2005: 253-257 |
7 | EE | Yehea I. Ismail,
Muhammad M. Khellah,
Maged Ghoneima,
James Tschanz,
Yibin Ye,
Vivek De:
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.
ISCAS (1) 2005: 592-595 |
6 | EE | James Tschanz,
Siva Narendra,
Ali Keshavarzi,
Vivek De:
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
ISCAS (1) 2005: 9-12 |
2004 |
5 | EE | Siva Narendra,
Vasantha Erraguntla,
James Tschanz,
Nitin Borkar:
Design Challenges in Sub-100nm High Performance Microprocessors.
VLSI Design 2004: 15-17 |
2003 |
4 | EE | Shekhar Borkar,
Tanay Karnik,
Siva Narendra,
James Tschanz,
Ali Keshavarzi,
Vivek De:
Parameter variations and impact on circuits and microarchitecture.
DAC 2003: 338-342 |
2002 |
3 | EE | Tanay Karnik,
Yibin Ye,
James Tschanz,
Liqiong Wei,
Steven M. Burns,
Venkatesh Govindarajulu,
Vivek De,
Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
DAC 2002: 486-491 |
2 | EE | Ali Keshavarzi,
James Tschanz,
Siva Narendra,
Vivek De,
W. Robert Daasch,
Kaushik Roy,
Manoj Sachdev,
Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Design & Test of Computers 19(5): 36-43 (2002) |
2001 |
1 | EE | James Tschanz,
Siva Narendra,
Zhanping Chen,
Shekhar Borkar,
Manoj Sachdev,
Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
ISLPED 2001: 147-152 |