Partha Pratim Chakrabarti
List of publications from the DBLP Bibliography Server - FAQ
2009 | ||
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113 | EE | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti: Inline Assertions - Embedding Formal Properties in a Test Bench. VLSI Design 2009: 71-76 |
112 | EE | Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti: Design intent coverage revisited. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
111 | EE | Sandip Aine, Rajeev Kumar, P. P. Chakrabarti: Adaptive parameter control of evolutionary algorithms to improve quality-time trade-off. Appl. Soft Comput. 9(2): 527-540 (2009) |
2008 | ||
110 | EE | Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan: A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. ATVA 2008: 222-227 |
109 | EE | Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan: Cohesive Coverage Management for Simulation and Formal Property Verification. ISVLSI 2008: 251-256 |
108 | EE | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti: Auxiliary state machines + context-triggered properties in verification. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008) |
107 | EE | S. K. Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar: Simulation-based verification using Temporally Attributed Boolean Logic. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008) |
106 | EE | Pravanjan Choudhury, Rajeev Kumar, P. P. Chakrabarti: Hybrid Scheduling of Dynamic Task Graphs with Selective Duplication for Multiprocessors under Memory and Time Constraints. IEEE Trans. Parallel Distrib. Syst. 19(7): 967-980 (2008) |
105 | EE | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta: Satisfiability Models for Maximum Transition Power. IEEE Trans. VLSI Syst. 16(8): 941-951 (2008) |
2007 | ||
104 | EE | Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta: Timing Analysis of Sequential Circuits Using Symbolic Event Propagation. ICCTA 2007: 151-157 |
103 | EE | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar: AWA* - A Window Constrained Anytime Heuristic Search Algorithm. IJCAI 2007: 2250-2255 |
102 | EE | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta: Bounded Delay Timing Analysis Using Boolean Satisfiability. VLSI Design 2007: 295-302 |
101 | EE | S. K. Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar: Simulation Based Verification using Temporally Attributed Boolean Logic. VLSI Design 2007: 57-62 |
100 | EE | Pravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar: Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors. VLSI Design 2007: 89-94 |
99 | EE | Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti: A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. VLSI Design 2007: 95-102 |
98 | EE | Tathagato Rai Dastidar, P. P. Chakrabarti: A verification system for transient response of analog circuits. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
97 | EE | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta: Event propagation for accurate circuit delay calculation using SAT. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
96 | EE | Dipankar Das, P. P. Chakrabarti, Rajeev Kumar: Functional verification of task partitioning for multiprocessor embedded systems. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
95 | EE | Abhishek Somani, P. P. Chakrabarti, Amit Patra: An Evolutionary Algorithm-Based Approach to Automated Design of Analog and RF Circuits Using Adaptive Normalized Cost Functions. IEEE Trans. Evolutionary Computation 11(3): 336-353 (2007) |
94 | EE | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar: An Automated Meta-Level Control Framework for Optimizing the Quality-Time Tradeoff of VLSI Algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1992-2008 (2007) |
93 | EE | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti: BUSpec: A framework for generation of verification aids for standard bus protocol specifications. Integration 40(3): 285-304 (2007) |
2006 | ||
92 | EE | Dipankar Das, Rajeev Kumar, P. P. Chakrabarti: Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications. APSEC 2006: 199-208 |
91 | EE | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti: Discovering the input assumptions in specification refinement coverage. ASP-DAC 2006: 13-18 |
90 | EE | Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti: What lies between design intent coverage and model checking? DATE 2006: 1217-1222 |
89 | EE | Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti: Synthesis of system verilog assertions. DATE Designers' Forum 2006: 70-75 |
88 | EE | Rajeev Kumar, Rahul Chaudhry, Dipankar Das, Vibha Rathi, S. K. Panda, P. P. Chakrabarti: SystemC Modeling and Validation of A RISC Processor System. FDL 2006: 189-197 |
87 | EE | Abhishek Somani, P. P. Chakrabarti, Amit Patra: A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits. ISCAS 2006 |
86 | EE | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti: Formal methods for checking realizability of coalitions in 3-party systems. MEMOCODE 2006: 198 |
85 | EE | Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta: A Framework for Estimating Peak Power in Gate-Level Circuits. PATMOS 2006: 573-582 |
84 | EE | Samik Das, P. P. Chakrabarti, Pallab Dasgupta: Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. VLSI Design 2006: 293-298 |
83 | EE | Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar: Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems. VLSI Design 2006: 677-682 |
82 | EE | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar: Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control. VLSI Design 2006: 683-688 |
81 | EE | Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar: Frame-Based Proportional Round-Robin. IEEE Trans. Computers 55(9): 1121-1129 (2006) |
80 | EE | Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni: Design-Intent Coverage - A New Paradigm for Formal Property Verification. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1922-1934 (2006) |
79 | EE | Arijit Mondal, P. P. Chakrabarti: Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1793-1814 (2006) |
2005 | ||
78 | EE | Sandip Aine, Rajeev Kumar, P. P. Chakrabarti: An Adaptive Framework for Solving Multiple Hard Problems Under Time Constraints. CIS (1) 2005: 57-64 |
77 | EE | Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra: Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits. DATE 2005: 1064-1069 |
76 | EE | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti: Multiobjective EA Approach for Improved Quality of Solutions for Spanning Tree Problem. EMO 2005: 811-825 |
75 | Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti: SAT based solutions for consistency problems in formal property specifications for open systems. ICCAD 2005: 885-888 | |
74 | Sandip Aine, Rajeev Kumar, P. P. Chakrabarti: Adaptive Control of Anytime Algorithm Parameters. IICAI 2005: 72-87 | |
73 | EE | Tathagato Rai Dastidar, P. P. Chakrabarti: A Verification System for Transient Response of Analog Circuits Using Model Checking. VLSI Design 2005: 195-200 |
72 | EE | Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix: Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. VLSI Design 2005: 201-206 |
71 | EE | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti: Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. VLSI Design 2005: 213-218 |
70 | EE | Abhishek Somani, P. P. Chakrabarti, Amit Patra: A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits. VLSI Design 2005: 535-538 |
69 | EE | Dipankar Das, Rajeev Kumar, P. P. Chakrabarti: Dictionary Based Code Compression for Variable Length Instruction Encodings. VLSI Design 2005: 545-550 |
68 | EE | Arnab Roy, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti: A framework for systematic validation and debugging of pipeline simulators. ACM Trans. Design Autom. Electr. Syst. 10(3): 462-491 (2005) |
67 | EE | Tathagato Rai Dastidar, P. P. Chakrabarti, Partha Ray: A synthesis system for analog circuits based on evolutionary search and topological reuse. IEEE Trans. Evolutionary Computation 9(2): 211-224 (2005) |
66 | EE | Rajeev Kumar, Amit Gupta, B. S. Pankaj, Mrinmoy Ghosh, P. P. Chakrabarti: Post-compilation optimization for multiple gains with pattern matching. SIGPLAN Notices 40(12): 14-23 (2005) |
2004 | ||
65 | EE | Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal: A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. DATE 2004: 1198-1203 |
64 | EE | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? DATE 2004: 668-669 |
63 | EE | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti: Improved Quality of Solutions for Multiobjective Spanning Tree Problem Using Distributed Evolutionary Algorithm. HiPC 2004: 494-503 |
62 | EE | Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni: Formal verification coverage: computing the coverage gap between temporal specifications. ICCAD 2004: 198-203 |
61 | EE | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti: Multiobjective Genetic Search for Spanning Tree Problem. ICONIP 2004: 218-223 |
60 | EE | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti: Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures. IWDC 2004: 102-113 |
59 | EE | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti: Distributed Evolutionary Algorithm Search for Multiobjective Spanning Tree Problem. IWDC 2004: 538 |
58 | EE | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti: The BUSpec platform for automated generation of verification aids for standard bus protocols. MEMOCODE 2004: 119-128 |
57 | EE | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti: Formal Verification of Modules under Real Time Environment Constraints. VLSI Design 2004: 103-108 |
56 | EE | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan: Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. VLSI Design 2004: 109-114 |
55 | EE | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti: The power of first-order quantification over states in branching and linear time temporal logics. Inf. Process. Lett. 91(5): 201-210 (2004) |
2003 | ||
54 | EE | Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti: Open computation tree logic with fairness. ISCAS (5) 2003: 249-252 |
53 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti: A Branching Time Temporal Framework for Quantitative Reasoning. J. Autom. Reasoning 30(2): 205-232 (2003) | |
2002 | ||
52 | EE | Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee: Formal verification of module interfaces against real time specifications. DAC 2002: 141-145 |
51 | EE | B. Rajendran, V. Kheterpal, A. Das, J. Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti: Timing analysis of tree-like RLC circuits. ISCAS (4) 2002: 838-841 |
50 | EE | Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti: Open Computation Tree Logic for Formal Verification of Modules. VLSI Design 2002: 735-740 |
49 | EE | Pallab Dasgupta, P. P. Chakrabarti, Arnab Dey, Sujoy Ghose, Wolfgang Bibel: Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques. IEEE Trans. Knowl. Data Eng. 14(2): 353-368 (2002) |
48 | EE | Anindya C. Patthak, Indrajit Bhattacharya, Anirban Dasgupta, Pallab Dasgupta, P. P. Chakrabarti: Quantified Computation Tree Logic. Inf. Process. Lett. 82(3): 123-129 (2002) |
2001 | ||
47 | EE | Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti: Abstraction of word-level linear arithmetic functions from bit-level component descriptions. DATE 2001: 4-8 |
46 | EE | S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti: Symbolic verification of Boolean constraints over partially specified functions. ISCAS (5) 2001: 113-116 |
45 | EE | Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti: Abstractions for model checking of event timings. ISCAS (5) 2001: 125-128 |
44 | EE | Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan: Min-max Computation Tree Logic. Artif. Intell. 127(1): 137-162 (2001) |
2000 | ||
43 | EE | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. IEEE Trans. VLSI Syst. 8(6): 747-750 (2000) |
42 | EE | Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti: Model checking on timed-event structures. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 601-611 (2000) |
1999 | ||
41 | EE | Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose: Controlling State Explosion in Static Simulation by Selective Composition. VLSI Design 1999: 226-231 |
40 | EE | Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti: An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. VLSI Design 1999: 294-299 |
39 | EE | Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti: Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams. VLSI Design 1999: 324- |
38 | P. P. Chakrabarti: Partial Precedence Constrained Scheduling. IEEE Trans. Computers 48(10): 1127-1130 (1999) | |
37 | EE | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: A design space exploration scheme for data-path synthesis. IEEE Trans. VLSI Syst. 7(3): 331-338 (1999) |
1998 | ||
36 | EE | Sudeshna Sarkar, P. P. Chakrabarti, Sujoy Ghose: A Framework for Learning in Search-Based Systems. IEEE Trans. Knowl. Data Eng. 10(4): 563-575 (1998) |
35 | Sudeshna Sarkar, P. P. Chakrabarti, Sujoy Ghose: Learning while solving problems in best first search. IEEE Transactions on Systems, Man, and Cybernetics, Part A 28(4): 535-541 (1998) | |
1997 | ||
34 | EE | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: Design Space Exploration for Data Path Synthesis. VLSI Design 1997: 166-173 |
1996 | ||
33 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: A New Competitive Algorithm for Agent Searching in Unknown Streets. FSTTCS 1996: 147-155 | |
32 | EE | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. VLSI Design 1996: 122-125 |
31 | EE | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: Searching Game Trees under a Partial Order. Artif. Intell. 82(1-2): 237-257 (1996) |
30 | EE | Chunduri Rama Mohan, Partha Pratim Chakrabarti: EARTH: combined state assignment of PLA-based FSM's targeting area and testability. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 727-731 (1996) |
29 | EE | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: Agent Search in Uniform b-Ary Trees: Multiple Goals and Unequal Costs. Inf. Process. Lett. 58(6): 311-318 (1996) |
28 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: Multiobjektive Heuristic Search in AND/OR Graphs. J. Algorithms 20(2): 282-311 (1996) | |
1995 | ||
27 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors. FSTTCS 1995: 22-36 | |
26 | EE | Chunduri Rama Mohan, Partha Pratim Chakrabarti: Combined optimization of area and testability during state assignment of PLA-based FSM's. VLSI Design 1995: 408-413 |
25 | EE | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening". Artif. Intell. 77(1): 173-176 (1995) |
24 | EE | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: Utility of Pathmax in Partial Order Heuristic Search. Inf. Process. Lett. 55(6): 317-322 (1995) |
1994 | ||
23 | EE | Chunduri Rama Mohan, Partha Pratim Chakrabarti: A new approach for factorizing FSM's. ICCAD 1994: 698-701 |
22 | Chunduri Rama Mohan, Partha Pratim Chakrabarti: A New Approach to Synthesis of PLA-Based FSM's. VLSI Design 1994: 373-378 | |
21 | Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar: Multiobjective Search in VLSI Design. VLSI Design 1994: 395-400 | |
20 | P. P. Chakrabarti: Algorithms for Searching Explicit AND/OR Graphs and their Applications to Problem Reduction Search. Artif. Intell. 65(2): 329-345 (1994) | |
19 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar: Agent Searching in a Tree and the Optimality of Iterative Deepening. Artif. Intell. 71(1): 195-208 (1994) | |
18 | U. K. Sarkar, P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Improving Greedy Algorithms by Lookahead-Search. J. Algorithms 16(1): 1-23 (1994) | |
1993 | ||
17 | Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose: Combining State Assignment with PLA Folding. VLSI Design 1993: 9-14 | |
1992 | ||
16 | Prabir K. Biswas, Jayanta Mukherjee, B. N. Chatterji, Partha Pratim Chakrabarti: Qualitative Description of Three-Dimensional Scenes. IJPRAI 6(4): 651-672 (1992) | |
15 | U. K. Sarkar, P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Effective Use of Memory in Iterative Deepening Search. Inf. Process. Lett. 42(1): 47-52 (1992) | |
14 | U. K. Sarkar, P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: A Simple 0.5-Bounded Greedy Algorithm for the 0/1 Knapsack Problem. Inf. Process. Lett. 42(3): 173-177 (1992) | |
13 | EE | P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Generalized best first search using single and multiple heuristics. Inf. Sci. 60(1-2): 145-175 (1992) |
12 | P. P. Chakrabarti, Sujoy Ghose: A General Best First Search Algorithm in AND/OR Graphs. J. Algorithms 13(2): 177-187 (1992) | |
1991 | ||
11 | U. K. Sarkar, P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Reducing Reexpansions in Iterative-Deepening Search by Controlling Cutoff Bounds. Artif. Intell. 50(2): 207-221 (1991) | |
10 | U. K. Sarkar, P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Multiple Stack Branch and Bound. Inf. Process. Lett. 37(1): 43-48 (1991) | |
1989 | ||
9 | U. K. Sarkar, P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Pruning by Upperbounds in Heuristic Search: Use of Approximate Algorithms. KBCS 1989: 451-461 | |
8 | P. P. Chakrabarti, Sujoy Ghose, Arup Acharya, S. C. De Sarkar: Heuristic Search in Restricted Memory. Artif. Intell. 41(2): 197-221 (1989) | |
7 | P. P. Chakrabarti, Sujoy Ghose, A. Pandey, S. C. De Sarkar: Increasing Search Efficiency Using Multiple Heuristics. Inf. Process. Lett. 30(1): 33-36 (1989) | |
6 | P. P. Chakrabarti, Sujoy Ghose, A. Pandey, S. C. De Sarkar: Increasing Search Efficiency Using Multiple Heuristics. Inf. Process. Lett. 32(5): 275-275 (1989) | |
1988 | ||
5 | EE | P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Best first search in and/or graphs. ACM Conference on Computer Science 1988: 256-261 |
1987 | ||
4 | P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Admissibility of A0* when Heuristics Overestimate. Artif. Intell. 34(1): 97-113 (1987) | |
3 | EE | Partha Pratim Das, P. P. Chakrabarti, Biswanath N. Chatterji: Generalized distances in digital geometry. Inf. Sci. 42(1): 51-67 (1987) |
2 | EE | Partha Pratim Das, P. P. Chakrabarti, Biswanath N. Chatterji: Distance functions in digital geometry. Inf. Sci. 42(2): 113-136 (1987) |
1986 | ||
1 | P. P. Chakrabarti, Sujoy Ghose, S. C. De Sarkar: Heuristic Search Through Islands. Artif. Intell. 29(3): 339-347 (1986) |