| 2007 |
| 13 | EE | Tiberiu Chelcea,
Girish Venkataramani,
Seth Copen Goldstein:
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis.
ASYNC 2007: 117-128 |
| 12 | EE | Girish Venkataramani,
Mihai Budiu,
Tiberiu Chelcea,
Seth Copen Goldstein:
Global Critical Path: A Tool for System-Level Timing Analysis.
DAC 2007: 783-786 |
| 11 | EE | Tiberiu Chelcea,
Girish Venkataramani,
Seth Copen Goldstein:
Self-Resetting Latches for Asynchronous Micro-Pipelines.
DAC 2007: 986-989 |
| 2006 |
| 10 | EE | Mahim Mishra,
Timothy J. Callahan,
Tiberiu Chelcea,
Girish Venkataramani,
Seth Copen Goldstein,
Mihai Budiu:
Tartan: evaluating spatial computation for whole program execution.
ASPLOS 2006: 163-174 |
| 9 | EE | Girish Venkataramani,
Tobias Bjerregaard,
Tiberiu Chelcea,
Seth Copen Goldstein:
Hardware compilation of application-specific memory-access interconnect.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 756-771 (2006) |
| 2005 |
| 8 | EE | Girish Venkataramani,
Tiberiu Chelcea,
Seth Copen Goldstein,
Tobias Bjerregaard:
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.
CODES+ISSS 2005: 231-236 |
| 2004 |
| 7 | EE | Mihai Budiu,
Girish Venkataramani,
Tiberiu Chelcea,
Seth Copen Goldstein:
Spatial computation.
ASPLOS 2004: 14-26 |
| 6 | EE | Tiberiu Chelcea,
Steven M. Nowick:
Robust interfaces for mixed-timing systems.
IEEE Trans. VLSI Syst. 12(8): 857-873 (2004) |
| 2002 |
| 5 | EE | Tiberiu Chelcea,
Steven M. Nowick:
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems.
DAC 2002: 405-410 |
| 4 | EE | Tiberiu Chelcea,
Steven M. Nowick,
Andrew Bardsley,
Doug Edwards:
A Burst-Mode Oriented Back-End for the Balsa Synthesis System.
DATE 2002: 330-337 |
| 3 | | Tiberiu Chelcea,
Steven M. Nowick:
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems.
IWLS 2002: 355-360 |
| 2001 |
| 2 | EE | Tiberiu Chelcea,
Steven M. Nowick:
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols.
DAC 2001: 21-26 |
| 2000 |
| 1 | EE | Tiberiu Chelcea,
Steven M. Nowick:
Low-Latency Asynchronous FIFO's Using Token Rings.
ASYNC 2000: 210- |