| 2009 |
|---|
| 181 | EE | Aida Todri,
Malgorzata Marek-Sadowska,
Francois Maire,
Christophe Matheron:
A study of decoupling capacitor effectiveness in power and ground grid networks.
ISQED 2009: 653-658 |
| 180 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 245-258 (2009) |
| 179 | EE | Yu-Min Kuo,
Ya-Ting Chang,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 456-460 (2009) |
| 2008 |
|---|
| 178 | EE | Hailin Jiang,
Malgorzata Marek-Sadowska:
Power gating scheduling for power/ground noise reduction.
DAC 2008: 980-985 |
| 177 | EE | Aida Todri,
Malgorzata Marek-Sadowska,
Joseph N. Kozhaya:
Power supply noise aware workload assignment for multi-core systems.
ICCAD 2008: 330-337 |
| 176 | EE | Aida Todri,
Malgorzata Marek-Sadowska:
A study of reliability issues in clock distribution networks.
ICCD 2008: 101-106 |
| 175 | EE | Shih-Hung Weng,
Yu-Min Kuo,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Timing analysis considering IR drop waveforms in power gating designs.
ICCD 2008: 532-537 |
| 174 | EE | Yi-Wei Lin,
Malgorzata Marek-Sadowska,
Wojciech Maly,
Andrzej Pfitzner,
Dominik Kasprowicz:
Is there always performance overhead for regular fabric?
ICCD 2008: 557-562 |
| 173 | EE | Nilesh A. Modi,
Malgorzata Marek-Sadowska:
ECO-Map: Technology remapping for post-mask ECO using simulated annealing.
ICCD 2008: 652-657 |
| 172 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis.
ISQED 2008: 246-253 |
| 171 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 932-945 (2008) |
| 2007 |
|---|
| 170 | EE | Wojciech Maly,
Yi-Wei Lin,
Malgorzata Marek-Sadowska:
OPC-Free and Minimally Irregular IC Design Style.
DAC 2007: 954-957 |
| 169 | EE | Yu-Shih Su,
Da-Chung Wang,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.
DAC 2007: 976-981 |
| 168 | EE | Yu-Min Kuo,
Ya-Ting Chang,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Engineering change using spare cells with constant insertion.
ICCAD 2007: 544-547 |
| 167 | EE | Aida Todri,
Malgorzata Marek-Sadowska,
Shih-Chieh Chang:
Analysis and optimization of power-gated ICs with multiple power gating configurations.
ICCAD 2007: 783-790 |
| 166 | EE | Aida Todri,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Electromigration and voltage drop aware power grid optimization for power gated ICs.
ISLPED 2007: 391-394 |
| 165 | EE | Hailin Jiang,
Malgorzata Marek-Sadowska:
Power-Gating Aware Floorplanning.
ISQED 2007: 853-860 |
| 164 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Timing-Aware Power-Noise Reduction in Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 527-541 (2007) |
| 2006 |
|---|
| 163 | EE | Hailin Jiang,
Malgorzata Marek-Sadowska:
Power/ground supply network optimization for power-gating.
ICCD 2006 |
| 162 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Zhiyuan Wang,
Kun-Han Tsai,
Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test.
ISQED 2006: 463-472 |
| 161 | EE | Chung-Kuan Tsai,
Malgorzata Marek-Sadowska:
Analysis of Process Variation's Effect on SRAM's Read Stability.
ISQED 2006: 603-610 |
| 160 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
Designing via-configurable logic blocks for regular fabric.
IEEE Trans. VLSI Syst. 14(1): 1-14 (2006) |
| 159 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics.
IEEE Trans. VLSI Syst. 14(9): 998-1009 (2006) |
| 158 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 558-575 (2006) |
| 157 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 611-624 (2006) |
| 2005 |
|---|
| 156 | EE | Hailin Jiang,
Kai Wang,
Malgorzata Marek-Sadowska:
Clock skew bounds estimation under power supply and process variations.
ACM Great Lakes Symposium on VLSI 2005: 332-336 |
| 155 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
A congestion-driven placement framework with local congestion prediction.
ACM Great Lakes Symposium on VLSI 2005: 488-493 |
| 154 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Skew-programmable clock design for FPGA and skew-aware placement.
FPGA 2005: 33-40 |
| 153 | | Yajun Ran,
Malgorzata Marek-Sadowska:
Via-configurable routing architectures and fast design mappability estimation for regular fabrics.
ICCAD 2005: 25-32 |
| 152 | | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Timing-aware power noise reduction in layout.
ICCAD 2005: 627-634 |
| 151 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement.
ICCD 2005: 31-37 |
| 150 | EE | Hailin Jiang,
Malgorzata Marek-Sadowska,
Sani R. Nassif:
Benefits and Costs of Power-Gating Technique.
ICCD 2005: 559-566 |
| 149 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
Wire length prediction-based technology mapping and fanout optimization.
ISPD 2005: 145-151 |
| 148 | EE | Bo Hu,
Yue Zeng,
Malgorzata Marek-Sadowska:
mFAR: fixed-points-addition-based VLSI placement algorithm.
ISPD 2005: 239-241 |
| 147 | EE | Chung-Kuan Tsai,
Malgorzata Marek-Sadowska:
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis.
ISQED 2005: 654-661 |
| 146 | EE | Kai Wang,
Malgorzata Marek-Sadowska:
On-chip power-supply network optimization using multigrid-based technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 407-417 (2005) |
| 145 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 762-772 (2005) |
| 144 | EE | Kai Wang,
Yajun Ran,
Hailin Jiang,
Malgorzata Marek-Sadowska:
General skew constrained clock network sizing based on sequential linear programming.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 773-782 (2005) |
| 143 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
Multilevel fixed-point-addition-based VLSI placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1188-1203 (2005) |
| 142 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Delay-fault diagnosis using timing information.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1315-1325 (2005) |
| 141 | EE | Yajun Ran,
Alex Kondratyev,
Kenneth H. Tseng,
Yosinori Watanabe,
Malgorzata Marek-Sadowska:
Eliminating false positives in crosstalk noise analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1406-1419 (2005) |
| 2004 |
|---|
| 140 | EE | Kai Wang,
Malgorzata Marek-Sadowska:
Buffer sizing for clock power minimization subject to general skew constraints.
DAC 2004: 159-164 |
| 139 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
On designing via-configurable cell blocks for regular fabrics.
DAC 2004: 198-203 |
| 138 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
Pre-layout wire length and congestion estimation.
DAC 2004: 582-587 |
| 137 | EE | Yajun Ran,
Alex Kondratyev,
Yosinori Watanabe,
Malgorzata Marek-Sadowska:
Eliminating False Positives in Crosstalk Noise Analysis.
DATE 2004: 1192-1197 |
| 136 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
Multilevel expansion-based VLSI placement with blockages.
ICCAD 2004: 558-564 |
| 135 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
An integrated design flow for a via-configurable gate array.
ICCAD 2004: 582-589 |
| 134 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Diagnosis of Hold Time Defects.
ICCD 2004: 192-199 |
| 133 | EE | Kai Wang,
Malgorzata Marek-Sadowska:
Potential Slack Budgeting with Clock Skew Optimization.
ICCD 2004: 265-271 |
| 132 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
The Magic of a Via-Configurable Regular Fabric.
ICCD 2004: 338-343 |
| 131 | EE | Kai Wang,
Malgorzata Marek-Sadowska:
Clock network sizing via sequential linear programming with time-domain analysis.
ISPD 2004: 182-189 |
| 130 | EE | Qinghua Liu,
Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency.
ISPD 2004: 198-203 |
| 129 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Delay Fault Diagnosis Using Timing Information.
ISQED 2004: 485-490 |
| 128 | EE | Luca Macchiarulo,
Shih-Min Shu,
Malgorzata Marek-Sadowska:
Pipelining Sequential Circuits with Wave Steering.
IEEE Trans. Computers 53(9): 1205-1210 (2004) |
| 127 | EE | Qinghua Liu,
Bo Hu,
Malgorzata Marek-Sadowska:
Individual wire-length prediction with application to timing-driven placement.
IEEE Trans. VLSI Syst. 12(10): 1004-1014 (2004) |
| 126 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction.
IEEE Trans. VLSI Syst. 12(10): 1028-1037 (2004) |
| 125 | EE | Chih-Wei Jim Chang,
Ming-Fu Hsiao,
Bo Hu,
Kai Wang,
Malgorzata Marek-Sadowska,
Chung-Kuan Cheng,
Sao-Jie Chen:
Fast postplacement optimization using functional symmetries.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 102-118 (2004) |
| 124 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
Fine granularity clustering-based placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 527-536 (2004) |
| 2003 |
|---|
| 123 | EE | Kai Wang,
Malgorzata Marek-Sadowska:
On-chip power supply network optimization using multigrid-based technique.
DAC 2003: 113-118 |
| 122 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement.
DAC 2003: 202-207 |
| 121 | EE | Bo Hu,
Yosinori Watanabe,
Alex Kondratyev,
Malgorzata Marek-Sadowska:
Gain-based technology mapping for discrete-size cell libraries.
DAC 2003: 574-579 |
| 120 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
Wire length prediction based clustering and its application in placement.
DAC 2003: 800-805 |
| 119 | EE | Donald Chai,
Alex Kondratyev,
Yajun Ran,
Kenneth H. Tseng,
Yosinori Watanabe,
Malgorzata Marek-Sadowska:
Temporofunctional crosstalk noise analysis.
DAC 2003: 860-863 |
| 118 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
Crosstalk noise in FPGAs.
DAC 2003: 944-949 |
| 117 | EE | Kai Wang,
Malgorzata Marek-Sadowska:
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique.
DATE 2003: 10850-10855 |
| 116 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Minimum-Area Sequential Budgeting for FPGA.
ICCAD 2003: 813-817 |
| 115 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests.
ICCD 2003: 198- |
| 114 | EE | Ming-Fu Hsiao,
Malgorzata Marek-Sadowska,
Sao-Jie Chen:
A crosstalk aware two-pin net router.
ISCAS (5) 2003: 485-488 |
| 113 | EE | Ming-Fu Hsiao,
Malgorzata Marek-Sadowska,
Sao-Jie Chen:
Minimizing coupling jitter by buffer resizing for coupled clock networks.
ISCAS (5) 2003: 509-512 |
| 112 | EE | Bo Hu,
Hailin Jiang,
Qinghua Liu,
Malgorzata Marek-Sadowska:
Synthesis and placement flow for gain-based programmable regular fabrics.
ISPD 2003: 197-203 |
| 111 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
Fine granularity clustering for large scale placement problems.
ISPD 2003: 67-74 |
| 110 | EE | Chung-Kuan Tsai,
Malgorzata Marek-Sadowska:
Modeling Crosstalk Induced Delay.
ISQED 2003: 189-194 |
| 109 | EE | Ming-Fu Hsiao,
Malgorzata Marek-Sadowska,
Sao-Jie Chen:
Minimizing Inter-Clock Coupling Jitter.
ISQED 2003: 333-338 |
| 108 | EE | Zhiyuan Wang,
Kun-Han Tsai,
Malgorzata Marek-Sadowska,
Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis.
ITC 2003: 329-338 |
| 107 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction.
SLIP 2003: 23-30 |
| 106 | EE | Qinghua Liu,
Bo Hu,
Malgorzata Marek-Sadowska:
Wire length prediction in constraint driven placement.
SLIP 2003: 99-105 |
| 105 | EE | Arindam Mukherjee,
Malgorzata Marek-Sadowska:
Clock and Power Gating with Timing Closure.
IEEE Design & Test of Computers 20(3): 32-39 (2003) |
| 104 | EE | Arindam Mukherjee,
Malgorzata Marek-Sadowska:
Wave steering to integrate logic and physical syntheses.
IEEE Trans. VLSI Syst. 11(1): 105-120 (2003) |
| 103 | EE | Amit Singh,
Arindam Mukherjee,
Luca Macchiarulo,
Malgorzata Marek-Sadowska:
PITIA: an FPGA for throughput-intensive applications.
IEEE Trans. VLSI Syst. 11(3): 354-363 (2003) |
| 102 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Forrest Brewer:
Buffer delay change in the presence of power and ground noise.
IEEE Trans. VLSI Syst. 11(3): 461-473 (2003) |
| 101 | EE | Chih-Wei Jim Chang,
Ming-Fu Hsiao,
Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 945-951 (2003) |
| 2002 |
|---|
| 100 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Forrest Brewer:
Coping with buffer delay change due to power and ground noise.
DAC 2002: 860-865 |
| 99 | EE | Arindam Mukherjee,
Kai Wang,
Lauren Hui Chen,
Malgorzata Marek-Sadowska:
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.
DATE 2002: 176-185 |
| 98 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska:
Closed-Form Crosstalk Noise Metrics for Physical Design Applications.
DATE 2002: 812-819 |
| 97 | EE | Amit Singh,
Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs.
FPGA 2002: 59-66 |
| 96 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
Congestion minimization during placement without estimation.
ICCAD 2002: 739-745 |
| 95 | EE | Chih-Wei Jim Chang,
Malgorzata Marek-Sadowska:
ATPG-based logic synthesis: an overview.
ICCAD 2002: 786-789 |
| 94 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska:
Incremental delay change due to crosstalk noise.
ISPD 2002: 120-125 |
| 93 | EE | Bo Hu,
Malgorzata Marek-Sadowska:
FAR: fixed-points addition & relaxation based placement.
ISPD 2002: 161-166 |
| 92 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska:
Efficient Closed-Form Crosstalk Delay Metrics.
ISQED 2002: 431-436 |
| 91 | EE | Amit Singh,
Malgorzata Marek-Sadowska:
FPGA interconnect planning.
SLIP 2002: 23-30 |
| 90 | EE | Amit Singh,
Ganapathy Parthasarathy,
Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs.
ACM Trans. Design Autom. Electr. Syst. 7(4): 643-663 (2002) |
| 2001 |
|---|
| 89 | EE | Chih-Wei Jim Chang,
Malgorzata Marek-Sadowska:
Who are the alternative wires in your neighborhood? (alternative wires identification without search).
ACM Great Lakes Symposium on VLSI 2001: 103-108 |
| 88 | EE | Amit Singh,
Arindam Mukherjee,
Malgorzata Marek-Sadowska:
Latency and Latch Count Minimization in Wave Steered Circuits.
DAC 2001: 383-388 |
| 87 | EE | Tong Xiao,
Malgorzata Marek-Sadowska:
Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification.
DAC 2001: 653-656 |
| 86 | EE | Chih-Wei Jim Chang,
Kai Wang,
Malgorzata Marek-Sadowska:
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques.
DAC 2001: 97-102 |
| 85 | EE | Chih-Wei Jim Chang,
Bo Hu,
Malgorzata Marek-Sadowska:
In-place delay constrained power optimization using functional symmetries.
DATE 2001: 377-382 |
| 84 | EE | Nobuo Funabiki,
Amit Singh,
Arindam Mukherjee,
Malgorzata Marek-Sadowska:
A Global Routing Technique for Wave-Steering Design Methodology.
DSD 2001: 430-437 |
| 83 | EE | Amit Singh,
Arindam Mukherjee,
Malgorzata Marek-Sadowska:
Interconnect pipelining in a throughput-intensive FPGA architecture.
FPGA 2001: 153-160 |
| 82 | EE | Amit Singh,
Ganapathy Parthasarathy,
Malgorzata Marek-Sadowska:
Interconnect Resource-Aware Placement for Hierarchical FPGAs.
ICCAD 2001: 132-136 |
| 81 | EE | Chih-Wei Jim Chang,
Malgorzata Marek-Sadowska:
Single-Pass Redundancy Addition and Removal.
ICCAD 2001: 606-609 |
| 80 | | Tong Xiao,
Malgorzata Marek-Sadowska:
Gate Sizing to Eliminate Crosstalk Induced Timing Violation.
ICCD 2001: 186-191 |
| 79 | EE | Ganapathy Parthasarathy,
Malgorzata Marek-Sadowska,
Arindam Mukherjee,
Amit Singh:
Interconnect complexity-aware FPGA placement using Rent's rule.
SLIP 2001: 115-121 |
| 78 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska:
Aggressor alignment for worst-case crosstalk noise.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 612-621 (2001) |
| 2000 |
|---|
| 77 | EE | Chih-Wei Jim Chang,
Chung-Kuan Cheng,
Peter Suaris,
Malgorzata Marek-Sadowska:
Fast post-placement rewiring using easily detectable functional symmetries.
DAC 2000: 286-289 |
| 76 | EE | Luca Macchiarulo,
Malgorzata Marek-Sadowska:
Wave-steering one-hot encoded FSMs.
DAC 2000: 357-360 |
| 75 | EE | Luca Macchiarulo,
Shih-Ming Shu,
Malgorzata Marek-Sadowska:
Wave Steered FSMs.
DATE 2000: 270-276 |
| 74 | EE | Amit Singh,
Luca Macchiarulo,
Arindam Mukherjee,
Malgorzata Marek-Sadowska:
A novel high throughput reconfigurable FPGA architecture.
FPGA 2000: 22-29 |
| 73 | EE | Tong Xiao,
Malgorzata Marek-Sadowska:
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis.
ICCD 2000: 115-120 |
| 72 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska:
Aggressor alignment for worst-case coupling noise.
ISPD 2000: 48-54 |
| 71 | EE | Tong Xiao,
Malgorzata Marek-Sadowska:
Efficient Delay Calculation in Presence of Crosstalk.
ISQED 2000: 491-498 |
| 70 | EE | Yu-Liang Wu,
Hongbing Fan,
Malgorzata Marek-Sadowska,
C. K. Wong:
OBDD Minimization Based on Two-Level Representation of Boolean Functions.
IEEE Trans. Computers 49(12): 1371-1379 (2000) |
| 69 | EE | Kun-Han Tsai,
Janusz Rajski,
Malgorzata Marek-Sadowska:
Star test: the theory and its applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1052-1064 (2000) |
| 1999 |
|---|
| 68 | EE | Tong Xiao,
Malgorzata Marek-Sadowska:
Crosstalk Reduction by Transistor Sizing.
ASP-DAC 1999: 137-140 |
| 67 | EE | Arindam Mukherjee,
Ranganathan Sudhakar,
Malgorzata Marek-Sadowska,
Stephen I. Long:
Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique.
DAC 1999: 466-471 |
| 66 | EE | Amit Singh,
Malgorzata Marek-Sadowska:
Circuit clustering using graph coloring.
ISPD 1999: 164-169 |
| 65 | | Kuo-Hui Tsai,
Tompson,
Janusz Rajski,
Malgorzata Marek-Sadowska:
STAR-ATPG: a high speed test pattern generator for large scan designs.
ITC 1999: 1021-1030 |
| 64 | EE | Ashok Vittal,
Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Kai-Ping Wang,
Sherry Yang:
Modeling Crosstalk in Resistive VLSI Interconnections.
VLSI Design 1999: 470-475 |
| 63 | | Douglas Chang,
Malgorzata Marek-Sadowska:
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.
IEEE Trans. Computers 48(6): 565-578 (1999) |
| 62 | | Shih-Chieh Chang,
Lukas P. P. P. van Ginneken,
Malgorzata Marek-Sadowska:
Circuit Optimization by Rewiring.
IEEE Trans. Computers 48(9): 962-970 (1999) |
| 61 | EE | Ashok Vittal,
Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Kai-Ping Wang,
Sherry Yang:
Crosstalk in VLSI interconnections.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1817-1824 (1999) |
| 60 | EE | Chih-Chang Lin,
Kuang-Chien Chen,
Malgorzata Marek-Sadowska:
Logic synthesis for engineering change.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 282-292 (1999) |
| 1998 |
|---|
| 59 | EE | Douglas Chang,
Kwang-Ting Cheng,
Malgorzata Marek-Sadowska,
Mike Tien-Chien Lee:
Functional Scan Chain Testing.
DATE 1998: 278- |
| 58 | EE | Douglas Chang,
Malgorzata Marek-Sadowska:
Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs.
FPGA 1998: 161-167 |
| 57 | EE | David Ihsin Cheng,
Kwang-Ting Cheng,
Deborah C. Wang,
Malgorzata Marek-Sadowska:
A hybrid methodology for switching activities estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 357-366 (1998) |
| 56 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng,
Mike Tien-Chien Lee:
Test-point insertion: scan paths through functional logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 838-851 (1998) |
| 55 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Mike Tien-Chien Lee,
Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 852-861 (1998) |
| 1997 |
|---|
| 54 | EE | Douglas Chang,
Mike Tien-Chien Lee,
Malgorzata Marek-Sadowska,
Takashi Aikyo,
Kwang-Ting Cheng:
A Test Synthesis Approach to Reducing BALLAST DFT Overhead.
DAC 1997: 466-471 |
| 53 | EE | Kun-Han Tsai,
Sybille Hellebrand,
Janusz Rajski,
Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation.
DAC 1997: 472-477 |
| 52 | EE | Yi-Min Jiang,
Angela Krstic,
Kwang-Ting Cheng,
Malgorzata Marek-Sadowska:
Post-Layout Logic Restructuring for Performance Optimization.
DAC 1997: 662-665 |
| 51 | EE | Douglas Chang,
Malgorzata Marek-Sadowska:
Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs.
FPGA 1997: 142-148 |
| 50 | EE | Marek A. Perkowski,
Malgorzata Marek-Sadowska,
Lech Józwiak,
Tadeusz Luba,
Stan Grygiel,
Miroslawa Nowicka,
Rahul Malvi,
Zhi Wang,
Jin S. Zhang:
Decomposition of Multiple-Valued Relations .
ISMVL 1997: 13-18 |
| 49 | EE | Stan Grygiel,
Marek A. Perkowski,
Malgorzata Marek-Sadowska,
Tadeusz Luba,
Lech Józwiak:
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations.
ISMVL 1997: 287-292 |
| 48 | | Kun-Han Tsai,
Malgorzata Marek-Sadowska,
Janusz Rajski:
Scan-Encoded Test Pattern Generation for BIST.
ITC 1997: 548-556 |
| 47 | | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms.
IEEE Trans. Computers 46(2): 173-186 (1997) |
| 46 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Crosstalk reduction for VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 290-298 (1997) |
| 45 | EE | Yu-Liang Wu,
Malgorzata Marek-Sadowska:
Routing for array-type FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 506-518 (1997) |
| 44 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska:
On designing universal logic blocks and their application to FPGA design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 519-527 (1997) |
| 43 | EE | Shih-Chieh Chang,
Kwang-Ting Cheng,
Nam Sung Woo,
Malgorzata Marek-Sadowska:
Postlayout logic restructuring using alternative wires.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 587-596 (1997) |
| 42 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Low-power buffered clock tree design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 965-975 (1997) |
| 1996 |
|---|
| 41 | EE | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Multilevel Logic Synthesis for Arithmetic Functions.
DAC 1996: 242-247 |
| 40 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng,
Mike Tien-Chien Lee:
Test Point Insertion: Scan Paths through Combinational Logic.
DAC 1996: 268-273 |
| 39 | EE | David Ihsin Cheng,
Kwang-Ting Cheng,
Deborah C. Wang,
Malgorzata Marek-Sadowska:
A New Hybrid Methodology for Power Estimation.
DAC 1996: 439-444 |
| 38 | EE | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Logic Synthesis for Testability.
Great Lakes Symposium on VLSI 1996: 118-121 |
| 37 | EE | Shih-Chieh Chang,
Lukas P. P. P. van Ginneken,
Malgorzata Marek-Sadowska:
Fast Boolean optimization by rewiring.
ICCAD 1996: 262-269 |
| 36 | EE | Ashok Vittal,
Hein Ha,
Forrest Brewer,
Malgorzata Marek-Sadowska:
Clock skew optimization for ground bounce control.
ICCAD 1996: 395-399 |
| 35 | | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Generalized Reed-Muller Forms as a Tool to Detect Symmetries.
IEEE Trans. Computers 45(1): 33-40 (1996) |
| 34 | EE | Yu-Liang Wu,
Shuji Tsukiyama,
Malgorzata Marek-Sadowska:
Graph based analysis of 2-D FPGA routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 33-44 (1996) |
| 33 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996) |
| 32 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
Perturb and simplify: multilevel Boolean network optimizer.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1494-1504 (1996) |
| 1995 |
|---|
| 31 | EE | Chih-Chang Lin,
David Ihsin Cheng,
Malgorzata Marek-Sadowska,
Kuang-Chien Chen:
Logic rectification and synthesis for engineering change.
ASP-DAC 1995 |
| 30 | EE | Yu-Liang Wu,
Malgorzata Marek-Sadowska:
Routing on regular segmented 2-D FPGAs.
ASP-DAC 1995 |
| 29 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Power Optimal Buffered Clock Tree Design.
DAC 1995: 497-502 |
| 28 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Power Distribution Topology Design.
DAC 1995: 503-507 |
| 27 | EE | Yu-Liang Wu,
Malgorzata Marek-Sadowska:
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing.
DAC 1995: 568-573 |
| 26 | EE | Chih-Chang Lin,
Kuang-Chien Chen,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
Logic Synthesis for Engineering Change.
DAC 1995: 647-652 |
| 25 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
An Efficient Algorithm for Local Don't Care Sets Calculation.
DAC 1995: 663-667 |
| 24 | EE | Chih-Chang Lin,
Mike Tien-Chien Lee,
Malgorzata Marek-Sadowska,
Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design methodology.
ICCAD 1995: 528-533 |
| 23 | EE | David Ihsin Cheng,
Chih-Chang Lin,
Malgorzata Marek-Sadowska:
Circuit partitioning with logic perturbation.
ICCAD 1995: 650-655 |
| 22 | EE | Malgorzata Marek-Sadowska,
Majid Sarrafzadeh:
The crossing distribution problem [IC layout].
IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 423-433 (1995) |
| 1994 |
|---|
| 21 | EE | Shih-Chieh Chang,
Kwang-Ting Cheng,
Nam Sung Woo,
Malgorzata Marek-Sadowska:
Layout Driven Logic Synthesis for FPGAs.
DAC 1994: 308-313 |
| 20 | EE | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Boolean Matching Using Generalized Reed-Muller Forms.
DAC 1994: 339-344 |
| 19 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Minimal Delay Interconnect Design Using Alphabetic Trees.
DAC 1994: 392-396 |
| 18 | | Yu-Liang Wu,
Malgorzata Marek-Sadowska:
An Efficient Router for 2-D Field Programmable Gate Arrays.
EDAC-ETC-EUROASIC 1994: 412-416 |
| 17 | | Shih-Chieh Chang,
David Ihsin Cheng,
Malgorzata Marek-Sadowska:
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions.
EDAC-ETC-EUROASIC 1994: 620-624 |
| 16 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Duane Gatlin:
Universal logic gate for FPGA design.
ICCAD 1994: 164-168 |
| 15 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Perturb and simplify: multi-level boolean network optimizer.
ICCAD 1994: 2-5 |
| 14 | | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms.
ISCAS 1994: 287-290 |
| 1993 |
|---|
| 13 | EE | Shen Lin,
Ernest S. Kuh,
Malgorzata Marek-Sadowska:
Stepwise equivalent conductance circuit simulation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 672-683 (1993) |
| 1992 |
|---|
| 12 | | Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Technology Mapping via Transformations of Function Graphs.
ICCD 1992: 159-162 |
| 1991 |
|---|
| 11 | | Malgorzata Marek-Sadowska,
Majid Sarrafzadeh:
The Crossing Distribution Problem.
ICCAD 1991: 528-531 |
| 1990 |
|---|
| 10 | EE | Shen Lin,
Malgorzata Marek-Sadowska,
Ernest S. Kuh:
Delay and Area Optimization in Standard-Cell Design.
DAC 1990: 349-352 |
| 9 | | Massoud Pedram,
Malgorzata Marek-Sadowska,
Ernest S. Kuh:
Floorplanning with Pin Assignment.
ICCAD 1990: 98-101 |
| 1989 |
|---|
| 8 | EE | Rajiv Dutta,
Malgorzata Marek-Sadowska:
Automatic Sizing of Power/Ground (P/G) Networks in VLSI.
DAC 1989: 783-786 |
| 7 | | Fillia Makedon,
Malgorzata Marek-Sadowska:
Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic.
ICCAL 1989: 359-378 |
| 1987 |
|---|
| 6 | EE | Malgorzata Marek-Sadowska:
Pad Assignment for Power Nets in VLSI Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 550-560 (1987) |
| 1985 |
|---|
| 5 | EE | Malgorzata Marek-Sadowska:
Two-dimensional router for double layer layout.
DAC 1985: 117-123 |
| 1984 |
|---|
| 4 | EE | Tom Tsan-Kuo Tarng,
Malgorzata Marek-Sadowska,
Ernest S. Kuh:
An Efficient Single-Row Routing Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 178-183 (1984) |
| 3 | EE | Malgorzata Marek-Sadowska:
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 184-190 (1984) |
| 2 | EE | Jeong-Tyng Li,
Malgorzata Marek-Sadowska:
Global Routing for Gate Array.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(4): 298-307 (1984) |
| 1983 |
|---|
| 1 | EE | Malgorzata Marek-Sadowska,
Tom Tsan-Kuo Tarng:
Single-Layer Routing for VLSI: Analysis and Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 246-259 (1983) |
