2009 |
34 | EE | Ying Zhou,
Rouwaida Kanj,
Kanak Agarwal,
Zhuo Li,
Rajiv V. Joshi,
Sani R. Nassif,
Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield.
ISQED 2009: 607-612 |
2008 |
33 | EE | Vivek Joshi,
Brian Cline,
Dennis Sylvester,
David Blaauw,
Kanak Agarwal:
Leakage power reduction using stress-enhanced layouts.
DAC 2008: 912-917 |
32 | EE | Vivek Joshi,
Brian Cline,
Dennis Sylvester,
David Blaauw,
Kanak Agarwal:
Stress aware layout optimization.
ISPD 2008: 168-174 |
31 | EE | Victoria Wang,
Kanak Agarwal,
Sani R. Nassif,
Kevin J. Nowka,
Dejan Markovic:
A Design Model for Random Process Variability.
ISQED 2008: 734-737 |
30 | EE | Kanak Agarwal,
Sani R. Nassif:
The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.
IEEE Trans. VLSI Syst. 16(1): 86-97 (2008) |
29 | EE | Dennis Sylvester,
Kanak Agarwal,
Saumil Shah:
Variability in nanometer CMOS: Impact, analysis, and minimization.
Integration 41(3): 319-339 (2008) |
2007 |
28 | EE | Kanak Agarwal,
Sani R. Nassif:
Characterizing Process Variation in Nanometer CMOS.
DAC 2007: 396-399 |
27 | EE | Kanak Agarwal,
Frank Liu:
Efficient computation of current flow in signal wires for reliability analysis.
ICCAD 2007: 741-746 |
26 | EE | Kanak Agarwal,
Kevin J. Nowka:
Dynamic Power Management by Combination of Dual Static Supply Voltages.
ISQED 2007: 85-92 |
25 | EE | H. Singh,
Kanak Agarwal,
Dennis Sylvester,
Kevin J. Nowka:
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.
IEEE Trans. VLSI Syst. 15(11): 1215-1224 (2007) |
24 | EE | Kanak Agarwal,
Rahul M. Rao,
Dennis Sylvester,
Richard B. Brown:
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.
IEEE Trans. VLSI Syst. 15(6): 613-623 (2007) |
2006 |
23 | EE | Kanak Agarwal,
Sani R. Nassif:
Statistical analysis of SRAM cell stability.
DAC 2006: 57-62 |
22 | EE | Emrah Acar,
Kanak Agarwal,
Sani R. Nassif:
Characterization of total chip leakage using inverse (reciprocal) gamma distribution.
ISCAS 2006 |
21 | EE | Sani R. Nassif,
Kanak Agarwal,
Emrah Acar:
Methods for estimating decoupling capacitance of nonswitching circuit blocks.
ISCAS 2006 |
20 | EE | Kanak Agarwal,
Kevin J. Nowka,
Harmander Deogun,
Dennis Sylvester:
Power Gating with Multiple Sleep Modes.
ISQED 2006: 633-637 |
19 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
Modeling and analysis of crosstalk noise in coupled RLC interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006) |
18 | EE | Kanak Agarwal,
Mridul Agarwal,
Dennis Sylvester,
David Blaauw:
Statistical interconnect metrics for physical-design optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006) |
2005 |
17 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw,
Anirudh Devgan:
Achieving continuous VT performance in a dual VT process.
ASP-DAC 2005: 393-398 |
16 | EE | Mridul Agarwal,
Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
Statistical modeling of cross-coupling effects in VLSI interconnects.
ASP-DAC 2005: 503-506 |
15 | EE | Ashish Srivastava,
Saumil Shah,
Kanak Agarwal,
Dennis Sylvester,
David Blaauw,
Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.
DAC 2005: 535-540 |
14 | EE | Rahul M. Rao,
Kanak Agarwal,
Dennis Sylvester,
Himanshu Kaul,
Richard B. Brown,
Sani R. Nassif:
Power-aware global signaling strategies.
ISCAS (1) 2005: 604-607 |
13 | EE | Rahul M. Rao,
Kanak Agarwal,
Anirudh Devgan,
Kevin J. Nowka,
Dennis Sylvester,
Richard B. Brown:
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.
ISQED 2005: 284-290 |
2004 |
12 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
A simplified transmission-line based crosstalk noise model for on-chip RLC wiring.
ASP-DAC 2004: 858-864 |
11 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw,
Frank Liu,
Sani R. Nassif,
Sarma B. K. Vrudhula:
Variational delay metrics for interconnect timing analysis.
DAC 2004: 381-384 |
10 | EE | Saumil Shah,
Kanak Agarwal,
Dennis Sylvester:
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters.
ICCD 2004: 138-143 |
9 | EE | Rahul M. Rao,
Kanak Agarwal,
Dennis Sylvester,
Richard B. Brown,
Kevin J. Nowka,
Sani R. Nassif:
Approaches to run-time and standby mode leakage reduction in global buses.
ISLPED 2004: 188-193 |
8 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
A library compatible driver output model for on-chip RLC transmission lines.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004) |
7 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
A simple metric for slew rate of RC circuits based on two circuit moments.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004) |
2003 |
6 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
An effective capacitance based driver output model for on-chip RLC interconnects.
DAC 2003: 376-381 |
5 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
Simple metrics for slew rate of RC circuits based on two circuit moments.
DAC 2003: 950-953 |
4 | EE | Shidhartha Das,
Kanak Agarwal,
David Blaauw,
Dennis Sylvester:
Optimal Inductance for On-chip RLC Interconnections.
ICCD 2003: 264- |
3 | EE | Takashi Sato,
Yu Cao,
Kanak Agarwal,
Dennis Sylvester,
Chenming Hu:
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003) |
2002 |
2 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw:
A library compatible driving point model for on-chip RLC interconnects.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69 |
1 | EE | Kanak Agarwal,
Yu Cao,
Takashi Sato,
Dennis Sylvester,
Chenming Hu:
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis.
VLSI Design 2002: 77- |