2009 |
21 | EE | María C. Molina,
Rafael Ruiz-Sautua,
Pedro Garcia-Repetto,
Román Hermida:
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 60-73 (2009) |
2008 |
20 | EE | Alberto A. Del Barrio,
María C. Molina,
Jose Manuel Mendias,
Esther Andres Perez,
Román Hermida,
Francisco Tirado:
Applying speculation techniques to implement functional units.
ICCD 2008: 74-80 |
2007 |
19 | EE | María C. Molina,
Rafael Ruiz-Sautua,
Jose Manuel Mendias,
Román Hermida:
Area optimization of multi-cycle operators in high-level synthesis.
DATE 2007: 449-454 |
18 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
CoRR abs/0710.4801: (2007) |
17 | EE | Rafael Ruiz-Sautua,
María C. Molina,
Jose Manuel Mendias:
Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1589-1601 (2007) |
2006 |
16 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Pre-synthesis optimization of multiplications to improve circuit performance.
DATE 2006: 1306-1311 |
15 | EE | María C. Molina,
Rafael Ruiz-Sautua,
Jose Manuel Mendias,
Román Hermida:
Bitwise scheduling to balance the computational cost of behavioral specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 31-46 (2006) |
2005 |
14 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Arrival time aware scheduling to minimize clock cycle length.
ASP-DAC 2005: 1018-1021 |
13 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.
DATE 2005: 1252-1257 |
12 | | Rafael Ruiz-Sautua,
María C. Molina,
Jose Manuel Mendias,
Román Hermida:
Performance-driven read-after-write dependencies softening in high-level synthesis.
ICCAD 2005: 7-12 |
2004 |
11 | EE | María C. Molina,
Rafael Ruiz-Sautua,
José M. Mendías,
Román Hermida:
Behavioural Bitwise Scheduling Based on Computational Effort Balancing.
DATE 2004: 684-685 |
10 | EE | María C. Molina,
Rafael Ruiz-Sautua,
José M. Mendías,
Román Hermida:
Behavioural Scheduling to Balance the Bit-Level Computational Effort.
ISVLSI 2004: 99-104 |
2003 |
9 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage.
DATE 2003: 10264-10269 |
8 | EE | María C. Molina,
Rafael Ruiz-Sautua,
José M. Mendías,
Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
PATMOS 2003: 617-627 |
7 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources.
Journal of Systems Architecture 49(12-15): 505-519 (2003) |
2002 |
6 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
High-level synthesis of multiple-precision circuitsindependent of data-objects length.
DAC 2002: 612-615 |
5 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Multiple-Precision Circuits Allocation Independent of Data-Objects Length.
DATE 2002: 909-915 |
4 | EE | José M. Mendías,
Román Hermida,
María C. Molina,
Olga Peñalba:
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.
DSD 2002: 308-315 |
3 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Bit-Level Allocation of Multiple-Precision Specifications.
DSD 2002: 385-392 |
2 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Bit-level scheduling of heterogeneous behavioural specifications.
ICCAD 2002: 602-608 |
2000 |
1 | EE | Olga Peñalba,
José M. Mendías,
María C. Molina:
Execution Condition Analysis in High Level Synthesis: A Unified Approach.
ISSS 2000: 73-78 |