| 2007 |
|---|
| 7 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Placement of 3D ICs with Thermal and Interlayer Via Considerations.
DAC 2007: 626-631 |
| 2006 |
|---|
| 6 | EE | Yong Zhan,
Brent Goplen,
Sachin S. Sapatnekar:
Electrothermal analysis and optimization techniques for nanoscale integrated circuits.
ASP-DAC 2006: 219-222 |
| 5 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 692-709 (2006) |
| 2005 |
|---|
| 4 | EE | Brent Goplen,
Prashant Saxena,
Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement.
DAC 2005: 503-508 |
| 3 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Thermal via placement in 3D ICs.
ISPD 2005: 167-174 |
| 2 | EE | Cristinel Ababei,
Yan Feng,
Brent Goplen,
Hushrav Mogal,
Tianpei Zhang,
Kia Bazargan,
Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits.
IEEE Design & Test of Computers 22(6): 520-531 (2005) |
| 2003 |
|---|
| 1 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach.
ICCAD 2003: 86-90 |
