Protecting Combinational Logic Synthesis Solutions.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2687-2696 (2006)|
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1077-1090 (2001)|
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.
ACM Trans. Design Autom. Electr. Syst. 5(2): 193-225 (2000)|
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections.
DAC 1999: 373-378|
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.
FPGA 1998: 27-34|
Intellectual property protection by watermarking combinational logic synthesis solutions.
ICCAD 1998: 194-198|
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.
FPGA 1997: 35-42|
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.
DAC 1996: 726-729|
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.
FPGA 1995: 68-74|