| 2006 |
|---|
| 9 | EE | Darko Kirovski,
Yean-Yow Hwang,
Miodrag Potkonjak,
Jason Cong:
Protecting Combinational Logic Synthesis Solutions.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2687-2696 (2006) |
| 2001 |
|---|
| 8 | EE | Jason Cong,
Yean-Yow Hwang:
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1077-1090 (2001) |
| 2000 |
|---|
| 7 | EE | Jason Cong,
Yean-Yow Hwang:
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.
ACM Trans. Design Autom. Electr. Syst. 5(2): 193-225 (2000) |
| 1999 |
|---|
| 6 | EE | Jason Cong,
Yean-Yow Hwang,
Songjie Xu:
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections.
DAC 1999: 373-378 |
| 1998 |
|---|
| 5 | EE | Jason Cong,
Yean-Yow Hwang:
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.
FPGA 1998: 27-34 |
| 4 | EE | Darko Kirovski,
Yean-Yow Hwang,
Miodrag Potkonjak,
Jason Cong:
Intellectual property protection by watermarking combinational logic synthesis solutions.
ICCAD 1998: 194-198 |
| 1997 |
|---|
| 3 | EE | Jason Cong,
Yean-Yow Hwang:
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.
FPGA 1997: 35-42 |
| 1996 |
|---|
| 2 | EE | Jason Cong,
Yean-Yow Hwang:
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.
DAC 1996: 726-729 |
| 1995 |
|---|
| 1 | EE | Jason Cong,
Yean-Yow Hwang:
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.
FPGA 1995: 68-74 |
