| 2009 |
|---|
| 207 | EE | Lara D. Oliver,
Krishnendu Chakrabarty,
Hisham Z. Massoud:
Dual-threshold pass-transistor logic design.
ACM Great Lakes Symposium on VLSI 2009: 291-296 |
| 206 | EE | Qiang Xu,
Yubin Zhang,
Krishnendu Chakrabarty:
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 205 | EE | Sandeep Kumar Goel,
Erik Jan Marinissen,
Anuja Sehgal,
Krishnendu Chakrabarty:
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.
IEEE Trans. Computers 58(3): 409-423 (2009) |
| 204 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 111-120 (2009) |
| 203 | EE | Zhanglei Wang,
Hongxia Fang,
Krishnendu Chakrabarty,
Michael Bienek:
Deviation-Based LFSR Reseeding for Test-Data Compression.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 259-271 (2009) |
| 2008 |
|---|
| 202 | EE | Tao Xu,
Krishnendu Chakrabarty:
Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips.
DAC 2008: 173-178 |
| 201 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty,
Richard Kacprowicz:
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs.
DATE 2008: 1103-1106 |
| 200 | EE | Anders Larsson,
Erik Larsson,
Krishnendu Chakrabarty,
Petru Eles,
Zebo Peng:
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns.
DATE 2008: 188-193 |
| 199 | EE | Tao Xu,
Krishnendu Chakrabarty,
Vamsee K. Pamula:
Design and optimization of a digital microfluidic biochip for protein crystallization.
ICCAD 2008: 297-301 |
| 198 | EE | Xiaoxia Wu,
Yibo Chen,
Krishnendu Chakrabarty,
Yuan Xie:
Test-access mechanism optimization for core-based three-dimensional SOCs.
ICCD 2008: 212-218 |
| 197 | EE | Tao Xu,
Krishnendu Chakrabarty:
Automated design of digital microfluidic lab-on-chip under pin-count constraints.
ISPD 2008: 190-198 |
| 196 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.
VTS 2008: 193-198 |
| 195 | EE | Mahmut Yilmaz,
Krishnendu Chakrabarty,
Mohammad Tehranipoor:
Test-Pattern Grading and Pattern Selection for Small-Delay Defects.
VTS 2008: 233-239 |
| 194 | EE | R. Iris Bahar,
Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 193 | EE | Anuja Sehgal,
Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Power-aware SoC test planning for effective utilization of port-scalable testers.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 192 | EE | Zhanglei Wang,
Krishnendu Chakrabarty:
Test Data Compression Using Selective Encoding of Scan Slices.
IEEE Trans. VLSI Syst. 16(11): 1429-1440 (2008) |
| 191 | EE | P. Y. Paik,
Vamsee K. Pamula,
Krishnendu Chakrabarty:
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics.
IEEE Trans. VLSI Syst. 16(4): 432-443 (2008) |
| 190 | EE | Tao Xu,
Krishnendu Chakrabarty:
A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1905-1917 (2008) |
| 189 | EE | Zhanglei Wang,
Krishnendu Chakrabarty:
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 352-365 (2008) |
| 188 | EE | Soheil Samii,
Mikko Selkälä,
Erik Larsson,
Krishnendu Chakrabarty,
Zebo Peng:
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 973-977 (2008) |
| 187 | EE | Nabil Badereddine,
Zhanglei Wang,
Patrick Girard,
Krishnendu Chakrabarty,
Arnaud Virazel,
Serge Pravossoudovitch,
Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electronic Testing 24(4): 353-364 (2008) |
| 186 | EE | Fei Su,
Krishnendu Chakrabarty:
High-level synthesis of digital microfluidic biochips.
JETC 3(4): (2008) |
| 185 | EE | R. Iris Bahar,
Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
JETC 4(2): (2008) |
| 184 | EE | Tao Xu,
Krishnendu Chakrabarty:
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.
JETC 4(3): (2008) |
| 183 | EE | Alvin R. Lebeck,
Krishnendu Chakrabarty:
Introduction to DAC 2007 special section.
JETC 4(3): (2008) |
| 2007 |
|---|
| 182 | EE | Sudarshan Bahukudumbi,
Sule Ozev,
Krishnendu Chakrabarty,
Vikram Iyengar:
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
ASP-DAC 2007: 823-828 |
| 181 | EE | Qiang Xu,
Yubin Zhang,
Krishnendu Chakrabarty:
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.
DAC 2007: 676-681 |
| 180 | EE | Tao Xu,
Krishnendu Chakrabarty:
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips.
DAC 2007: 948-953 |
| 179 | EE | Zhanglei Wang,
Krishnendu Chakrabarty,
Seongmoon Wang:
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
DATE 2007: 201-206 |
| 178 | EE | Tao Xu,
Krishnendu Chakrabarty:
A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays.
DATE 2007: 552-557 |
| 177 | | Krishnendu Chakrabarty:
Design and Test of Microfluidic Biochips.
DDECS 2007: 17 |
| 176 | EE | Zhanglei Wang,
Krishnendu Chakrabarty,
Michael Bienek:
A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.
European Test Symposium 2007: 125-130 |
| 175 | EE | Tao Xu,
Krishnendu Chakrabarty:
Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips.
European Test Symposium 2007: 63-68 |
| 174 | EE | Tong Zhou,
Romit Roy Choudhury,
Peng Ning,
Krishnendu Chakrabarty:
Privacy-Preserving Detection of Sybil Attacks in Vehicular Ad Hoc Networks.
MobiQuitous 2007: 1-8 |
| 173 | EE | Amit Kumar,
Krishnendu Chakrabarty,
Chunduri Rama Mohan:
An ECO Technique for Removing Crosstalk Violations in Clock Networks.
VLSI Design 2007: 283-288 |
| 172 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.
VLSI Design 2007: 459-464 |
| 171 | EE | Tao Xu,
Krishnendu Chakrabarty,
Fei Su:
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips.
VLSI Design 2007: 647-652 |
| 170 | EE | Lei Li,
Zhanglei Wang,
Krishnendu Chakrabarty:
Scan-BIST based on cluster analysis and the encoding of repeating sequences.
ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
| 169 | EE | Fei Su,
Krishnendu Chakrabarty,
Vamsee K. Pamula:
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
CoRR abs/0710.4672: (2007) |
| 168 | EE | Fei Su,
Krishnendu Chakrabarty:
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
CoRR abs/0710.4673: (2007) |
| 167 | EE | Anuja Sehgal,
Fang Liu,
Sule Ozev,
Krishnendu Chakrabarty:
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
CoRR abs/0710.4686: (2007) |
| 166 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules
CoRR abs/0710.4797: (2007) |
| 165 | EE | Krishnendu Chakrabarty,
Roland Thewes:
Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms.
IEEE Design & Test of Computers 24(1): 8-9 (2007) |
| 164 | EE | Anuja Sehgal,
Krishnendu Chakrabarty:
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.
IEEE Trans. Computers 56(1): 120-133 (2007) |
| 163 | EE | Yi Zou,
Krishnendu Chakrabarty:
Distributed Mobility Management for Target Tracking in Mobile Sensor Networks.
IEEE Trans. Mob. Comput. 6(8): 872-887 (2007) |
| 162 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Wafer-Level Modular Testing of Core-Based SoCs.
IEEE Trans. VLSI Syst. 15(10): 1144-1154 (2007) |
| 161 | EE | Qiang Xu,
Nicola Nicolici,
Krishnendu Chakrabarty:
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1539-1547 (2007) |
| 160 | EE | Yi Zou,
Krishnendu Chakrabarty:
Redundancy Analysis and a Distributed Self-Organization Protocol for Fault-Tolerant Wireless Sensor Networks.
IJDSN 3(3): 243-272 (2007) |
| 159 | EE | Zhanglei Wang,
Krishnendu Chakrabarty:
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics.
J. Electronic Testing 23(2-3): 145-161 (2007) |
| 158 | EE | Fei Su,
William L. Hwang,
Arindam Mukherjee,
Krishnendu Chakrabarty:
Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips.
J. Electronic Testing 23(2-3): 219-233 (2007) |
| 157 | EE | Tao Xu,
William L. Hwang,
Fei Su,
Krishnendu Chakrabarty:
Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints.
JETC 3(3): (2007) |
| 156 | EE | Krishnendu Chakrabarty,
Sachin S. Sapatnekar:
Editorial to special issue DAC 2006.
JETC 3(3): (2007) |
| 2006 |
|---|
| 155 | EE | Lara D. Oliver,
Krishnendu Chakrabarty,
Hisham Z. Massoud:
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.
ACM Great Lakes Symposium on VLSI 2006: 105-110 |
| 154 | EE | Tao Xu,
Krishnendu Chakrabarty:
Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips.
CODES+ISSS 2006: 112-117 |
| 153 | EE | William L. Hwang,
Fei Su,
Krishnendu Chakrabarty:
Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*.
DAC 2006: 925-930 |
| 152 | EE | Zhanglei Wang,
Krishnendu Chakrabarty,
Michael Gössel:
Test set enrichment using a probabilistic fault model and the theory of output deviations.
DATE 2006: 1270-1275 |
| 151 | EE | Anuja Sehgal,
Sandeep Kumar Goel,
Erik Jan Marinissen,
Krishnendu Chakrabarty:
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.
DATE 2006: 285-290 |
| 150 | EE | Fei Su,
William L. Hwang,
Krishnendu Chakrabarty:
Droplet routing in the synthesis of digital microfluidic biochips.
DATE 2006: 323-328 |
| 149 | EE | Krishnendu Chakrabarty:
Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.
DFT 2006 |
| 148 | EE | Krishnendu Chakrabarty:
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD.
ICCD 2006 |
| 147 | EE | Fei Su,
Sule Ozev,
Krishnendu Chakrabarty:
Concurrent testing of digital microfluidics-based biochips.
ACM Trans. Design Autom. Electr. Syst. 11(2): 442-464 (2006) |
| 146 | EE | Fei Su,
Krishnendu Chakrabarty:
Module placement for fault-tolerant microfluidics-based biochips.
ACM Trans. Design Autom. Electr. Syst. 11(3): 682-710 (2006) |
| 145 | EE | Anuja Sehgal,
Sule Ozev,
Krishnendu Chakrabarty:
Test infrastructure design for mixed-signal SOCs with wrapped analog cores.
IEEE Trans. VLSI Syst. 14(3): 292-304 (2006) |
| 144 | EE | Ying Zhang,
Krishnendu Chakrabarty:
A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 111-125 (2006) |
| 143 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2502-2512 (2006) |
| 142 | EE | Fei Su,
Krishnendu Chakrabarty:
Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2944-2953 (2006) |
| 141 | EE | Fei Su,
Krishnendu Chakrabarty,
Richard B. Fair:
Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 211-223 (2006) |
| 140 | EE | Fei Su,
Sule Ozev,
Krishnendu Chakrabarty:
Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems.
J. Electronic Testing 22(2): 199-210 (2006) |
| 139 | EE | Fei Su,
Krishnendu Chakrabarty:
Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy.
JETC 2(2): 104-128 (2006) |
| 2005 |
|---|
| 138 | EE | Yasumi Doi,
Seiji Kajihara,
Xiaoqing Wen,
Lei Li,
Krishnendu Chakrabarty:
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.
ASP-DAC 2005: 59-64 |
| 137 | EE | Krishnendu Chakrabarty,
Fei Su:
System-level design automation tools for digital microfluidic biochips.
CODES+ISSS 2005: 201-206 |
| 136 | EE | Qiang Xu,
Nicola Nicolici,
Krishnendu Chakrabarty:
Multi-frequency wrapper design and optimization for embedded cores under average power constraints.
DAC 2005: 123-128 |
| 135 | EE | Fei Su,
Krishnendu Chakrabarty:
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips.
DAC 2005: 825-830 |
| 134 | EE | Lei Li,
Krishnendu Chakrabarty:
Hybrid BIST Based on Repeating Sequences and Cluster Analysis.
DATE 2005: 1142-1147 |
| 133 | EE | Fei Su,
Krishnendu Chakrabarty,
Vamsee K. Pamula:
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration.
DATE 2005: 1196-1201 |
| 132 | EE | Fei Su,
Krishnendu Chakrabarty:
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips.
DATE 2005: 1202-1207 |
| 131 | EE | Anuja Sehgal,
Fang Liu,
Sule Ozev,
Krishnendu Chakrabarty:
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.
DATE 2005: 50-55 |
| 130 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules.
DATE 2005: 840-845 |
| 129 | EE | Yi Zou,
Krishnendu Chakrabarty:
Fault-Tolerant Self-organization in Sensor Networks.
DCOSS 2005: 191-205 |
| 128 | EE | Enkelejda Tafaj,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.
DFT 2005: 544-551 |
| 127 | | Anuja Sehgal,
Krishnendu Chakrabarty:
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs.
ICCAD 2005: 88-93 |
| 126 | | Krishnendu Chakrabarty,
J. E. Chen:
A cocktail approach on random access scan toward low power and high efficiency test.
ICCAD 2005: 94-99 |
| 125 | EE | Anuja Sehgal,
Sule Ozev,
Krishnendu Chakrabarty:
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.
ICCD 2005: 137-142 |
| 124 | EE | Krishnendu Chakrabarty:
Design, Testing, and Applications of Digital Microfluidics-Based Biochips.
VLSI Design 2005: 221-226 |
| 123 | EE | Lei Li,
Krishnendu Chakrabarty,
Seiji Kajihara,
Shivakumar Swaminathan:
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.
VLSI Design 2005: 53-58 |
| 122 | EE | Fei Su,
Krishnendu Chakrabarty:
Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips.
VTS 2005: 321-326 |
| 121 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty:
Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems.
ACM Trans. Embedded Comput. Syst. 4(1): 141-167 (2005) |
| 120 | EE | Harshavardhan Sabbineni,
Krishnendu Chakrabarty:
Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks.
IEEE Trans. Computers 54(1): 36-46 (2005) |
| 119 | EE | Yi Zou,
Krishnendu Chakrabarty:
A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks.
IEEE Trans. Computers 54(8): 978-991 (2005) |
| 118 | EE | Mohammad Tehranipoor,
Mehrdad Nourani,
Krishnendu Chakrabarty:
Nine-coded compression technique for testing embedded cores in SoCs.
IEEE Trans. VLSI Syst. 13(6): 719-731 (2005) |
| 117 | EE | Chunsheng Liu,
Krishnendu Chakrabarty:
Design and analysis of compact dictionaries for diagnosis in scan-BIST.
IEEE Trans. VLSI Syst. 13(8): 979-984 (2005) |
| 116 | EE | Krishnendu Chakrabarty,
Vikram Iyengar,
Mark D. Krasniewski:
Test planning for modular testing of hierarchical SOCs.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 435-448 (2005) |
| 115 | EE | Krishnendu Chakrabarty,
Jun Zeng:
Design automation for microfluidics-based biochips.
JETC 1(3): 186-223 (2005) |
| 2004 |
|---|
| 114 | EE | Ying Zhang,
Robert P. Dick,
Krishnendu Chakrabarty:
Energy-aware deterministic fault tolerance in distributed real-time embedded systems.
DAC 2004: 550-555 |
| 113 | EE | Ying Zhang,
Krishnendu Chakrabarty:
Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems.
DATE 2004: 1170-1175 |
| 112 | EE | Mohammad H. Tehranipour,
Mehrdad Nourani,
Krishnendu Chakrabarty:
Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression.
DATE 2004: 1284-1289 |
| 111 | EE | Anuja Sehgal,
Krishnendu Chakrabarty:
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.
DATE 2004: 422-427 |
| 110 | EE | Fei Su,
Krishnendu Chakrabarty:
Architectural-level synthesis of digital microfluidics-based biochips.
ICCAD 2004: 223-228 |
| 109 | EE | Chunsheng Liu,
Kumar N. Dwarakanath,
Krishnendu Chakrabarty,
Ronald D. Blanton:
Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.
ISVLSI 2004: 173-178 |
| 108 | EE | Anuja Sehgal,
Sandeep Kumar Goel,
Erik Jan Marinissen,
Krishnendu Chakrabarty:
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
ITC 2004: 1203-1212 |
| 107 | EE | Fei Su,
Krishnendu Chakrabarty:
Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays.
ITC 2004: 883-892 |
| 106 | EE | Yi Zou,
Krishnendu Chakrabarty:
Sensor deployment and target localization in distributed sensor networks.
ACM Trans. Embedded Comput. Syst. 3(1): 61-91 (2004) |
| 105 | EE | Ying Zhang,
Krishnendu Chakrabarty:
Dynamic adaptation for fault tolerance and power management in embedded real-time systems.
ACM Trans. Embedded Comput. Syst. 3(2): 336-360 (2004) |
| 104 | EE | Chunsheng Liu,
Krishnendu Chakrabarty:
Compact Dictionaries for Fault Diagnosis in Scan-BIST.
IEEE Trans. Computers 53(6): 775-780 (2004) |
| 103 | EE | Qishi Wu,
Nageswara S. V. Rao,
Jacob Barhen,
S. Sitharama Iyengar,
Vijay K. Vaishnavi,
Hairong Qi,
Krishnendu Chakrabarty:
On Computing Mobile Agent Routes for Data Fusion in Distributed Sensor Networks.
IEEE Trans. Knowl. Data Eng. 16(6): 740-753 (2004) |
| 102 | EE | Anuja Sehgal,
Vikram Iyengar,
Krishnendu Chakrabarty:
SOC test planning using virtual test access architectures.
IEEE Trans. VLSI Syst. 12(12): 1263-1276 (2004) |
| 101 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty:
Network flow techniques for dynamic voltage scaling in hard real-time systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1385-1398 (2004) |
| 100 | EE | Chunsheng Liu,
Krishnendu Chakrabarty:
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1447-1459 (2004) |
| 99 | EE | Tianhao Zhang,
Krishnendu Chakrabarty,
Richard B. Fair:
Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 843-858 (2004) |
| 98 | EE | Lei Li,
Krishnendu Chakrabarty:
Test set embedding for deterministic BIST using a reconfigurable interconnection network.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1289-1305 (2004) |
| 97 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.
J. Electronic Testing 20(2): 199-212 (2004) |
| 96 | EE | Michael Gössel,
Krishnendu Chakrabarty,
Vitalij Ocheretnij,
Andreas Leininger:
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.
J. Electronic Testing 20(6): 611-622 (2004) |
| 95 | EE | Lei Li,
Krishnendu Chakrabarty:
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression.
J. Electronic Testing 20(6): 667-670 (2004) |
| 94 | EE | Yi Zou,
Krishnendu Chakrabarty:
Uncertainty-aware and coverage-oriented deployment for sensor networks.
J. Parallel Distrib. Comput. 64(7): 788-798 (2004) |
| 2003 |
|---|
| 93 | EE | Vamsee K. Pamula,
Krishnendu Chakrabarty:
Cooling of integrated circuits using droplet-based microfluidics.
ACM Great Lakes Symposium on VLSI 2003: 84-87 |
| 92 | EE | Anuja Sehgal,
Vikram Iyengar,
Mark D. Krasniewski,
Krishnendu Chakrabarty:
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.
DAC 2003: 738-743 |
| 91 | EE | Dhiraj K. Pradhan,
Chunsheng Liu,
Krishnendu Chakrabarty:
EBIST: A Novel Test Generator with Built-In Fault Detection Capability.
DATE 2003: 10224-10229 |
| 90 | EE | Chunsheng Liu,
Krishnendu Chakrabarty:
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis.
DATE 2003: 10230-10237 |
| 89 | EE | Ying Zhang,
Krishnendu Chakrabarty:
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems.
DATE 2003: 10918-10925 |
| 88 | EE | Vikram Iyengar,
Anshuman Chandra,
Sharon Schweizer,
Krishnendu Chakrabarty:
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.
DATE 2003: 11188-11190 |
| 87 | EE | Ying Zhang,
Krishnendu Chakrabarty:
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems.
DFT 2003: 320-327 |
| 86 | EE | Ying Zhang,
Krishnendu Chakrabarty,
Vishnu Swaminathan:
Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems.
ICCAD 2003: 209-214 |
| 85 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty:
Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems.
ICCAD 2003: 21-25 |
| 84 | EE | Anuja Sehgal,
Sule Ozev,
Krishnendu Chakrabarty:
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers.
ICCAD 2003: 95-99 |
| 83 | EE | Seiji Kajihara,
Yasumi Doi,
Lei Li,
Krishnendu Chakrabarty:
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.
ICCD 2003: 387-396 |
| 82 | EE | Yi Zou,
Krishnendu Chakrabarty:
Sensor Deployment and Target Localization Based on Virtual Forces.
INFOCOM 2003 |
| 81 | EE | Chunsheng Liu,
Krishnendu Chakrabarty:
Compact Dictionaries for Fault Diagnosis in BIST.
ISQED 2003: 105-110 |
| 80 | EE | Fei Su,
Sule Ozev,
Krishnendu Chakrabarty:
Testing of Droplet-Based Microelectrofluidic Systems.
ITC 2003: 1192-1200 |
| 79 | EE | Lei Li,
Krishnendu Chakrabarty:
Deterministic BIST Based on a Reconfigurable Interconnection Network.
ITC 2003: 460-469 |
| 78 | EE | Yi Zou,
Krishnendu Chakrabarty:
Energy-Aware Target Localization in Wireless Sensor Networks.
PerCom 2003: 60- |
| 77 | EE | Lei Li,
Krishnendu Chakrabarty:
Test Data Compression Using Dictionaries with Fixed-Length Indices.
VTS 2003: 219-224 |
| 76 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Mark D. Krasniewski,
Gopind N. Kumar:
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs.
VTS 2003: 299-312 |
| 75 | EE | Lei Li,
Krishnendu Chakrabarty,
Nur A. Touba:
Test data compression using dictionaries with selective entries and fixed-length indices.
ACM Trans. Design Autom. Electr. Syst. 8(4): 470-490 (2003) |
| 74 | EE | Yi Zou,
Krishnendu Chakrabarty:
Target localization based on energy considerations in distributed sensor networks.
Ad Hoc Networks 1(2-3): 261-272 (2003) |
| 73 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers 52(12): 1619-1632 (2003) |
| 72 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.
IEEE Trans. Computers 52(8): 1076-1088 (2003) |
| 71 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
A unified approach to reduce SOC test data volume, scan power and testing time.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 352-363 (2003) |
| 70 | EE | Chunsheng Liu,
Krishnendu Chakrabarty:
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 593-604 (2003) |
| 69 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Efficient test access mechanism optimization for system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 635-643 (2003) |
| 68 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty:
Energy-conscious, deterministic I/O device scheduling in hard real-time systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 847-858 (2003) |
| 2002 |
|---|
| 67 | EE | Alexej Dmitriev,
Michael Gössel,
Krishnendu Chakrabarty:
Robust Space Compaction of Test Responses.
Asian Test Symposium 2002: 254-259 |
| 66 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
Asian Test Symposium 2002: 320- |
| 65 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty:
Pruning-based energy-optimal device scheduling for hard real-time systems.
CODES 2002: 175-180 |
| 64 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes.
DAC 2002: 673-678 |
| 63 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
DAC 2002: 685-690 |
| 62 | EE | Chunsheng Liu,
Krishnendu Chakrabarty,
Michael Gössel:
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment.
DATE 2002: 382-386 |
| 61 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Efficient Wrapper/TAM Co-Optimization for Large SOCs.
DATE 2002: 491-498 |
| 60 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression.
DATE 2002: 598-603 |
| 59 | EE | Vishnu Swaminathan,
Charles B. Schweizer,
Krishnendu Chakrabarty,
Amil A. Patel:
Experiences in Implementing an Energy-Driven Task Scheduler in RT-Linux.
IEEE Real Time Technology and Applications Symposium 2002: 229-238 |
| 58 | EE | Vikram Iyengar,
Sandeep Kumar Goel,
Erik Jan Marinissen,
Krishnendu Chakrabarty:
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
ITC 2002: 1159-1168 |
| 57 | EE | Erik Jan Marinissen,
Vikram Iyengar,
Krishnendu Chakrabarty:
A Set of Benchmarks fo Modular Testing of SOCs.
ITC 2002: 519-528 |
| 56 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.
VTS 2002: 253-258 |
| 55 | EE | Anshuman Chandra,
Krishnendu Chakrabarty,
Rafael A. Medina:
How Effective are Compression Codes for Reducing Test Data Volume?
VTS 2002: 91-96 |
| 54 | | Krishnendu Chakrabarty,
Erik Jan Marinissen:
How Useful are the ITC 02 SoC Test Benchmarks?
IEEE Design & Test of Computers 19(5): 120, 119 (2002) |
| 53 | EE | Krishnendu Chakrabarty,
S. Sitharama Iyengar,
Hairong Qi,
Eungchun Cho:
Grid Coverage for Surveillance and Target Location in Distributed Sensor Networks.
IEEE Trans. Computers 51(12): 1448-1453 (2002) |
| 52 | EE | Vikram Iyengar,
Krishnendu Chakrabarty:
Test Bus Sizing for System-on-a-Chip.
IEEE Trans. Computers 51(5): 449-459 (2002) |
| 51 | EE | Bhargab B. Bhattacharya,
Alexej Dmitriev,
Michael Gössel,
Krishnendu Chakrabarty:
Synthesis of single-output space compactors for scan-based sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1171-1179 (2002) |
| 50 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Low-power scan testing and test data compression forsystem-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 597-604 (2002) |
| 49 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Test data compression and decompression based on internal scanchains and Golomb coding.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 715-722 (2002) |
| 48 | EE | Tianhao Zhang,
Krishnendu Chakrabarty,
Richard B. Fair:
Design of reconfigurable composite microsystems based on hardware/software codesign principles.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 987-995 (2002) |
| 47 | EE | Vikram Iyengar,
Krishnendu Chakrabarty:
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1088-1094 (2002) |
| 46 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
J. Electronic Testing 18(2): 213-230 (2002) |
| 45 | EE | Krishnendu Chakrabarty:
Guest Editorial.
J. Electronic Testing 18(4-5): 363 (2002) |
| 2001 |
|---|
| 44 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty:
Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems.
ASP-DAC 2001: 251 |
| 43 | EE | Bhargab B. Bhattacharya,
Alexej Dmitriev,
Michael Gössel,
Krishnendu Chakrabarty:
Synthesis of single-output space compactors with application to scan-based IP cores.
ASP-DAC 2001: 496-502 |
| 42 | EE | Vishnu Swaminathan,
Krishnendu Chakrabarty,
S. Sitharama Iyengar:
Dynamic I/O power management for hard real-time systems.
CODES 2001: 237-242 |
| 41 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip.
DAC 2001: 166-169 |
| 40 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding.
DATE 2001: 145-149 |
| 39 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Test wrapper and test access mechanism co-optimization for system-on-chip.
ITC 2001: 1023-1032 |
| 38 | EE | Krishnendu Chakrabarty,
S. Sitharama Iyengar,
Hairong Qi,
Eungchun Cho:
Coding Theory Framework for Target Location in Distributed Sensor Networks.
ITCC 2001: 130- |
| 37 | EE | Krishnendu Chakrabarty,
Andrew Exnicios,
Rajatish Mukherjee:
Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test.
VLSI Design 2001: 431- |
| 36 | EE | Vikram Iyengar,
Krishnendu Chakrabarty:
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.
VTS 2001: 368-374 |
| 35 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression.
VTS 2001: 42-47 |
| 34 | EE | A. Morozov,
Michael Gössel,
Krishnendu Chakrabarty,
Bhargab B. Bhattacharya:
Design of Parameterizable Error-Propagating Space Compactors for Response Observation.
VTS 2001: 48-53 |
| 33 | EE | Krishnendu Chakrabarty:
Optimal test access architectures for system-on-a-chip.
ACM Trans. Design Autom. Electr. Syst. 6(1): 26-49 (2001) |
| 32 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Test Resource Partitioning for SOCs.
IEEE Design & Test of Computers 18(5): 80-91 (2001) |
| 31 | EE | Jie Ding,
Krishnendu Chakrabarty,
Richard B. Fair:
Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1463-1468 (2001) |
| 30 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 355-368 (2001) |
| 29 | | Hairong Qi,
S. Sitharama Iyengar,
Krishnendu Chakrabarty:
Multiresolution data integration using mobile agents in distributed sensor networks.
IEEE Transactions on Systems, Man, and Cybernetics, Part C 31(3): 383-391 (2001) |
| 28 | EE | Shivakumar Swaminathan,
Krishnendu Chakrabarty:
On Using Twisted-Ring Counters for Test Set Embedding in BIST.
J. Electronic Testing 17(6): 529-542 (2001) |
| 2000 |
|---|
| 27 | EE | Krishnendu Chakrabarty:
Design of system-on-a-chip test access architectures under place-and-route and power constraints.
DAC 2000: 432-437 |
| 26 | | Hiroshi Date,
Vikram Iyengar,
Krishnendu Chakrabarty,
Makoto Sugihara:
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
PDPTA 2000 |
| 25 | EE | Anshuman Chandra,
Krishnendu Chakrabarty:
Test Data Compression for System-on-a-Chip Using Golomb Codes.
VTS 2000: 113-120 |
| 24 | EE | Krishnendu Chakrabarty:
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming.
VTS 2000: 127-136 |
| 23 | EE | Markus Seuring,
Krishnendu Chakrabarty:
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions.
VTS 2000: 213-220 |
| 22 | EE | Krishnendu Chakrabarty,
Brian T. Murray,
Vikram Iyengar:
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
IEEE Trans. VLSI Syst. 8(5): 633-636 (2000) |
| 21 | EE | Krishnendu Chakrabarty:
Test scheduling for core-based systems using mixed-integer linearprogramming.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1163-1174 (2000) |
| 1999 |
|---|
| 20 | EE | Krishnendu Chakrabarty:
Test scheduling for core-based systems.
ICCAD 1999: 391-394 |
| 19 | EE | Krishnendu Chakrabarty,
Brian T. Murray,
Vikram Iyengar:
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.
VTS 1999: 22-27 |
| 18 | EE | Mark G. Karpovsky,
Krishnendu Chakrabarty,
Lev B. Levitin,
Dimiter R. Avresky:
On the Covering of Vertices for Fault Diagnosis in Hypercubes.
Inf. Process. Lett. 69(2): 99-103 (1999) |
| 17 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Brian T. Murray:
Deterministic Built-in Pattern Generation for Sequential Circuits.
J. Electronic Testing 15(1-2): 97-114 (1999) |
| 1998 |
|---|
| 16 | EE | Vikram Iyengar,
Krishnendu Chakrabarty,
Brian T. Murray:
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.
VTS 1998: 418-423 |
| 15 | | Krishnendu Chakrabarty,
Brian T. Murray,
John P. Hayes:
Optimal Zero-Aliasing Space Compaction of Test Responses.
IEEE Trans. Computers 47(11): 1171-1187 (1998) |
| 14 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Zero-aliasing space compaction of test responses using multiple parity signatures.
IEEE Trans. VLSI Syst. 6(2): 309-313 (1998) |
| 13 | EE | Krishnendu Chakrabarty,
Brian T. Murray:
Design of built-in test generator circuits using width compression.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1044-1051 (1998) |
| 12 | EE | Krishnendu Chakrabarty:
Zero-aliasing space compaction using linear compactors with bounded overhead.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 452-457 (1998) |
| 11 | | Mark G. Karpovsky,
Krishnendu Chakrabarty,
Lev B. Levitin:
On a New Class of Codes for Identifying Vertices in Graphs.
IEEE Transactions on Information Theory 44(2): 599-611 (1998) |
| 1997 |
|---|
| 10 | | Krishnendu Chakrabarty,
Jian Liu,
Minyao Zhu,
Brian T. Murray:
Test Width Compression for Built-In Self Testing.
ITC 1997: 328-337 |
| 9 | EE | Krishnendu Chakrabarty,
John P. Hayes:
On the quality of accumulator-based compaction of test responses.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 916-922 (1997) |
| 8 | EE | Vikram Iyengar,
Krishnendu Chakrabarty:
An Efficient Finite-State Machine Implementation of Huffman Decoders.
Inf. Process. Lett. 64(6): 271-275 (1997) |
| 1996 |
|---|
| 7 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Test response compaction using multiplexed parity trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1399-1408 (1996) |
| 6 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Balance testing and balance-testable design of logic circuits.
J. Electronic Testing 8(1): 71-86 (1996) |
| 1995 |
|---|
| 5 | | Krishnendu Chakrabarty,
Brian T. Murray,
John P. Hayes:
Optimal Space Compaction of Test Responses.
ITC 1995: 834-843 |
| 4 | EE | Krishnendu Chakrabarty,
John P. Hayes:
Cumulative balance testing of logic circuits.
IEEE Trans. VLSI Syst. 3(1): 72-83 (1995) |
| 1994 |
|---|
| 3 | EE | Krishnendu Chakrabarty,
John P. Hayes:
DFBT: A Design-for-Testability Method Based on Balance Testing.
DAC 1994: 351-357 |
| 2 | | Krishnendu Chakrabarty,
John P. Hayes:
Efficient Test-Response Compression for Multiple-Output Cicuits.
ITC 1994: 501-510 |
| 1993 |
|---|
| 1 | | Krishnendu Chakrabarty,
John P. Hayes:
Balance Testing of Logic Circuits.
FTCS 1993: 350-359 |
