| 2009 |
|---|
| 127 | EE | Ewout Martens,
Georges G. E. Gielen:
ANTIGONE: Top-down creation of analog-to-digital converter architectures.
Integration 42(1): 10-23 (2009) |
| 2008 |
|---|
| 126 | EE | Georges G. E. Gielen,
P. De Wit,
E. Maricau,
J. Loeckx,
J. Martin-Martinez,
Ben Kaczer,
Guido Groeseneken,
R. Rodríguez,
M. Nafría:
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies.
DATE 2008: 1322-1327 |
| 125 | EE | David Binkley,
Helmut E. Graeb,
Georges G. E. Gielen,
Jaijeet S. Roychowdhury:
From Transistor to PLL - Analogue Design and EDA Methods.
DATE 2008 |
| 124 | EE | Trent McConaghy,
Pieter Palmers,
Georges G. E. Gielen,
Michiel Steyaert:
Automated extraction of expert knowledge in analog topology selection and sizing.
ICCAD 2008: 392-395 |
| 123 | EE | Peng Gao,
Trent McConaghy,
Georges G. E. Gielen:
Importance sampled circuit learning ensembles for robust analog IC design.
ICCAD 2008: 396-399 |
| 122 | EE | Peng Gao,
Trent McConaghy,
Georges G. E. Gielen:
ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis.
ICES 2008: 11-21 |
| 121 | EE | Hans Danneels,
Marian Verhelst,
Pieter Palmers,
Wim Vereecken,
Bruno Boury,
Wim Dehaene,
Michiel Steyaert,
Georges G. E. Gielen:
A low-power mixing DAC IR-UWB-receiver.
ISCAS 2008: 2697-2700 |
| 120 | EE | Minghu Jiang,
Georges G. E. Gielen:
Analysis of quantization effects on high-order function neural networks.
Appl. Intell. 28(1): 51-67 (2008) |
| 119 | EE | Ewout Martens,
Georges G. E. Gielen:
Classification of analog synthesis tools based on their architecture selection mechanisms.
Integration 41(2): 238-252 (2008) |
| 2007 |
|---|
| 118 | | Georges G. E. Gielen:
2007 International Conference on Computer-Aided Design (ICCAD'07), November 5-8, 2007, San Jose, CA, USA
IEEE 2007 |
| 117 | EE | Georges G. E. Gielen:
Future trends for wireless communication frontends in nanometer CMOS.
ACM Great Lakes Symposium on VLSI 2007: 600-605 |
| 116 | EE | Georges G. E. Gielen:
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies.
ASP-DAC 2007: 432-437 |
| 115 | EE | Trent McConaghy,
Pieter Palmers,
Georges G. E. Gielen,
Michiel Steyaert:
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.
DAC 2007: 944-947 |
| 114 | EE | Tom Eeckelaert,
Raf Schoofs,
Georges G. E. Gielen,
Michiel Steyaert,
Willy M. C. Sansen:
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
DATE 2007: 81-86 |
| 113 | EE | Mustafa Badaroglu,
Geert Van der Plas,
Piet Wambacq,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
Scalable Gate-Level Models for Power and Timing Analysis.
ISCAS 2007: 2938-2941 |
| 112 | EE | Trent McConaghy,
Tom Eeckelaert,
Georges G. E. Gielen:
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming
CoRR abs/0710.4630: (2007) |
| 111 | EE | Georges G. E. Gielen,
Wim Dehaene,
Phillip Christie,
Dieter Draxelmayr,
Edmond Janssens,
Karen Maex,
Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
CoRR abs/0710.4709: (2007) |
| 110 | EE | Georges G. E. Gielen,
Donatella Sciuto:
Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference].
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 405-407 (2007) |
| 2006 |
|---|
| 109 | | Georges G. E. Gielen:
Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
European Design and Automation Association, Leuven, Belgium 2006 |
| 108 | | Georges G. E. Gielen:
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006
European Design and Automation Association, Leuven, Belgium 2006 |
| 107 | EE | Tom Eeckelaert,
Raf Schoofs,
Georges G. E. Gielen,
Michiel Steyaert,
Willy M. C. Sansen:
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.
DAC 2006: 25-30 |
| 106 | EE | Trent McConaghy,
Georges G. E. Gielen:
Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns.
DATE 2006: 269-274 |
| 105 | EE | Ewout Martens,
Georges G. E. Gielen:
Top-down heterogeneous synthesis of analog and mixed-signal systems.
DATE 2006: 275-280 |
| 104 | EE | Ewout Martens,
Georges G. E. Gielen:
Generic Behavioral Modeling of Analog and Mixed-Signal Systems.
FDL 2006: 15-23 |
| 103 | EE | Trent McConaghy,
Georges G. E. Gielen:
Canonical form functions as a simple means for genetic programming to evolve human-interpretable functions.
GECCO 2006: 855-862 |
| 102 | EE | Trent McConaghy,
Georges G. E. Gielen:
Automation in mixed-signal design: challenges and solutions in the wake of the nano era.
ICCAD 2006: 461-463 |
| 101 | EE | Ewout Martens,
Georges G. E. Gielen:
A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers.
ISCAS 2006 |
| 100 | EE | Alkis A. Hatzopoulos,
Stefanos Stefanou,
Georges G. E. Gielen,
Dominique Schreurs:
Assessment of parameter extraction methods for integrated inductor design and model validation.
ISCAS 2006 |
| 99 | EE | Mustafa Badaroglu,
Geert Van der Plas,
Piet Wambacq,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
SWAN: high-level simulation methodology for digital substrate noise generation.
IEEE Trans. VLSI Syst. 14(1): 23-33 (2006) |
| 98 | EE | Ewout Martens,
Georges G. E. Gielen:
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 924-932 (2006) |
| 97 | EE | Mustafa Badaroglu,
Kris Tiri,
Geert Van der Plas,
Piet Wambacq,
Ingrid Verbauwhede,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1146-1154 (2006) |
| 2005 |
|---|
| 96 | EE | Huiying Yang,
Mukesh Ranjan,
Wim Verhaegen,
Mengmeng Ding,
Ranga Vemuri,
Georges G. E. Gielen:
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams.
ASP-DAC 2005: 230-235 |
| 95 | EE | Georges G. E. Gielen,
Trent McConaghy,
Tom Eeckelaert:
Performance space modeling for hierarchical synthesis of analog integrated circuits.
DAC 2005: 881-886 |
| 94 | EE | Tom Eeckelaert,
Trent McConaghy,
Georges G. E. Gielen:
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces.
DATE 2005: 1070-1075 |
| 93 | EE | Trent McConaghy,
Tom Eeckelaert,
Georges G. E. Gielen:
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.
DATE 2005: 1082-1087 |
| 92 | EE | Ewout Martens,
Georges G. E. Gielen:
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series.
DATE 2005: 120-125 |
| 91 | EE | Georges G. E. Gielen,
Wim Dehaene,
Phillip Christie,
Dieter Draxelmayr,
Edmond Janssens,
Karen Maex,
Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
DATE 2005: 36-42 |
| 90 | EE | Trent McConaghy,
Georges G. E. Gielen:
Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization.
ISCAS (2) 2005: 1298-1301 |
| 89 | EE | Ewout Martens,
Georges G. E. Gielen:
Behavioral modeling and simulation of weakly nonlinear sampled-data systems.
ISCAS (3) 2005: 2247-2250 |
| 88 | EE | Trent McConaghy,
Georges G. E. Gielen:
IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming.
ISCAS (5) 2005: 5170-5173 |
| 87 | EE | Didier Van Reeth,
Georges G. E. Gielen:
A CAD Platform for Sensor Interfaces in Low-Power Applications.
PATMOS 2005: 374-381 |
| 86 | EE | Mustafa Badaroglu,
Piet Wambacq,
Geert Van der Plas,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 65-76 (2005) |
| 2004 |
|---|
| 85 | EE | Ewout Martens,
Georges G. E. Gielen:
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models.
ASP-DAC 2004: 51-56 |
| 84 | EE | Geert Van der Plas,
Mustafa Badaroglu,
Gerd Vandersteen,
Petr Dobrovolný,
Piet Wambacq,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
DAC 2004: 854-859 |
| 83 | EE | Ewout Martens,
Georges G. E. Gielen:
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design.
DATE 2004: 436-441 |
| 82 | EE | Tholom Kiely,
Georges G. E. Gielen:
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines.
DATE 2004: 448-453 |
| 81 | EE | Mukesh Ranjan,
Wim Verhaegen,
Anuradha Agarwal,
Hemanth Sampath,
Ranga Vemuri,
Georges G. E. Gielen:
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.
DATE 2004: 604-609 |
| 80 | EE | Mustafa Badaroglu,
Piet Wambacq,
Geert Van der Plas,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
Digital Ground Bounce Reduction by Phase Modulation of the Clock.
DATE 2004: 88-93 |
| 79 | | Tao Chen,
Georges G. E. Gielen:
Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters.
ISCAS (1) 2004: 293-296 |
| 78 | EE | João Ramos,
Kenneth Francken,
Georges G. E. Gielen,
Michiel Steyaert:
Knowledge- and optimization-based design of RF power amplifiers.
ISCAS (1) 2004: 629-632 |
| 77 | EE | Minghu Jiang,
Georges G. E. Gielen:
Backpropagation Analysis of the Limited Precision on High-Order Function Neural Networks.
ISNN (1) 2004: 305-310 |
| 76 | EE | Minghu Jiang,
Dafan Liu,
Beixing Deng,
Georges G. E. Gielen:
A Bayesian Classifier by Using the Adaptive Construct Algorithm of the RBF Networks.
ISNN (1) 2004: 876-881 |
| 75 | EE | Georges G. E. Gielen,
Kenneth Francken,
Ewout Martens,
Martin Vogels:
An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 389-399 (2004) |
| 2003 |
|---|
| 74 | EE | Martin Vogels,
Georges G. E. Gielen:
Architectural selection of A/D converters.
DAC 2003: 974-977 |
| 73 | EE | Ewout Martens,
Georges G. E. Gielen:
A Model of Computation for Continuous-Time ?-? Modulators.
DATE 2003: 10162-10167 |
| 72 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors.
DATE 2003: 10238-10243 |
| 71 | EE | Tom Eeckelaert,
Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
Generalized Posynomial Performance Modeling.
DATE 2003: 10250-10255 |
| 70 | EE | Bart De Smedt,
Georges G. E. Gielen:
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits.
DATE 2003: 10256-10263 |
| 69 | EE | Wolfgang Eberle,
Gerd Vandersteen,
Piet Wambacq,
Stéphane Donnay,
Georges G. E. Gielen,
Hugo De Man:
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
DATE 2003: 10642-10649 |
| 68 | EE | Martin Vogels,
Georges G. E. Gielen:
Figure of Merit Based Selection of A/D Converters.
DATE 2003: 11090-11091 |
| 67 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
A Generalized Method for Computing Oscillator Phase Noise Spectra.
ICCAD 2003: 247-250 |
| 66 | EE | Tao Chen,
Georges G. E. Gielen:
Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters.
ISCAS (1) 2003: 973-976 |
| 65 | | Minghu Jiang,
Georges G. E. Gielen,
Bo Zhang,
Zhensheng Luo:
Fast Learning Algorithms for Feedforward Neural Networks.
Appl. Intell. 18(1): 37-54 (2003) |
| 64 | EE | H. Alan Mantooth,
Georges G. E. Gielen:
Guest editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(2): 121-123 (2003) |
| 63 | EE | Bart De Smedt,
Georges G. E. Gielen:
WATSON: design space boundary exploration and model generation for analog and RFIC design.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(2): 213-224 (2003) |
| 62 | EE | Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 517-534 (2003) |
| 61 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1017-1026 (2003) |
| 60 | EE | Kenneth Francken,
Georges G. E. Gielen:
A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1049-1061 (2003) |
| 59 | EE | Minghu Jiang,
Georges G. E. Gielen:
The Effects of Quantization on Multi-Layer Feedforward Neural Networks.
IJPRAI 17(4): 637-661 (2003) |
| 2002 |
|---|
| 58 | EE | Mustafa Badaroglu,
Kris Tiri,
Stéphane Donnay,
Piet Wambacq,
Hugo De Man,
Ingrid Verbauwhede,
Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
DAC 2002: 399-404 |
| 57 | EE | Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits.
DAC 2002: 431-436 |
| 56 | EE | Ovidiu Bajdechi,
Johan H. Huijsing,
Georges G. E. Gielen:
Optimal design of delta-sigma ADCs by design space exploration.
DAC 2002: 443-448 |
| 55 | EE | Jan Vandenbussche,
K. Uyttenhove,
Erik Lauwers,
Michiel Steyaert,
Georges G. E. Gielen:
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter.
DAC 2002: 449-454 |
| 54 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators.
DAC 2002: 536-541 |
| 53 | EE | Kenneth Francken,
Martin Vogels,
Ewout Martens,
Georges G. E. Gielen:
DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators.
DATE 2002: 1110 |
| 52 | EE | Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics.
DATE 2002: 268-273 |
| 51 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices.
DATE 2002: 279-284 |
| 50 | EE | Jan Vandenbussche,
Erik Lauwers,
K. Uyttenhove,
Michiel Steyaert,
Georges G. E. Gielen:
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter.
DATE 2002: 357-361 |
| 49 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
On the difference between two widely publicized methods for analyzing oscillator phase behavior.
ICCAD 2002: 229-233 |
| 48 | EE | Kenneth Francken,
Martin Vogels,
Ewout Martens,
Georges G. E. Gielen:
A behavioral simulation tool for continuous-time delta sigma modulators.
ICCAD 2002: 234-239 |
| 47 | EE | Martin Vogels,
Kenneth Francken,
Ewout Martens,
Georges G. E. Gielen:
Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration.
ISCAS (4) 2002: 237-240 |
| 46 | EE | Francky Leyn,
Erik Lauwers,
Martin Vogels,
Georges G. E. Gielen,
Willy M. C. Sansen:
Regression criteria and their application in different modeling cases.
ISCAS (5) 2002: 85-8 |
| 45 | EE | Erik Lauwers,
Georges G. E. Gielen:
Power estimation methods for analog circuits for architectural exploration of integrated systems.
IEEE Trans. VLSI Syst. 10(2): 155-162 (2002) |
| 44 | EE | Carl De Ranter,
Geert Van der Plas,
Michiel Steyaert,
Georges G. E. Gielen,
Willy M. C. Sansen:
CYCLONE: automated design and layout of RF LC-oscillators.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1161-1170 (2002) |
| 43 | EE | Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
Circuit simplification for the symbolic analysis of analogintegrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 395-407 (2002) |
| 42 | EE | Geert Van der Plas,
Jan Vandenbussche,
Georges G. E. Gielen,
Willy M. C. Sansen:
A layout synthesis methodology for array-type analog blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 645-661 (2002) |
| 41 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1011-1024 (2002) |
| 40 | EE | Minghu Jiang,
Georges G. E. Gielen,
Beixing Deng,
Xiaoyan Zhu:
A fast learning algorithm for time-delay neural networks.
Inf. Sci. 148(1-4): 27-39 (2002) |
| 39 | | Minghu Jiang,
Xiaoyan Zhu,
Georges G. E. Gielen,
Elliott Drábek,
Ying Xia,
Gang Tan,
Ta Bao:
Braille to print translations for Chinese.
Information & Software Technology 44(2): 91-100 (2002) |
| 38 | EE | Georges G. E. Gielen:
Editorial.
Integration 33(1-2): 1-2 (2002) |
| 2001 |
|---|
| 37 | EE | Wim Verhaegen,
Georges G. E. Gielen:
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits.
DAC 2001: 139-144 |
| 36 | EE | Georges G. E. Gielen,
Mike Sottak,
Mike Murray,
Linda Kaye,
Maria del Mar Hershenson,
Kenneth S. Kundert,
Philippe Magarshack,
Akria Matsuzawa,
Ronald A. Rohrer,
Ping Yang:
Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?
DAC 2001: 419 |
| 35 | EE | Piet Vanassche,
Georges G. E. Gielen,
Willy M. C. Sansen:
Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model.
DATE 2001: 169-175 |
| 34 | EE | Mustafa Badaroglu,
Marc van Heijningen,
Vincent Gravot,
Stéphane Donnay,
Hugo De Man,
Georges G. E. Gielen,
Marc Engels,
Ivo Bolsens:
High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
DATE 2001: 326-330 |
| 33 | EE | Georges G. E. Gielen,
B. Sorensen,
H. Casier,
Philippe Magarshack,
J. Rodriguez:
Design challenges and emerging EDA solutions in mixed-signal IC design.
DATE 2001: 694-695 |
| 32 | EE | Peter J. Vancorenland,
Geert Van der Plas,
Michiel Steyaert,
Georges G. E. Gielen,
Willy M. C. Sansen:
A Layout-Aware Synthesis Methodology for RF Circuits.
ICCAD 2001: 358- |
| 31 | EE | Domine Leenaerts,
Rob A. Rutenbar,
Georges G. E. Gielen:
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.
ICCAD 2001 |
| 30 | EE | Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing.
ICCAD 2001: 70-74 |
| 29 | EE | Geert Van der Plas,
Geert Debyser,
Francky Leyn,
Koen Lampaert,
Jan Vandenbussche,
Georges G. E. Gielen,
Willy M. C. Sansen,
Petar Veselinovic,
Domine Leenaerts:
AMGIE-A synthesis environment for CMOS analog integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1037-1058 (2001) |
| 2000 |
|---|
| 28 | EE | Carl De Ranter,
B. De Muer,
Geert Van der Plas,
Peter J. Vancorenland,
Michiel Steyaert,
Georges G. E. Gielen,
Willy M. C. Sansen:
CYCLONE: automated design and layout of RF LC-oscillators.
DAC 2000: 11-14 |
| 27 | EE | Geert Van der Plas,
Jan Vandenbussche,
Walter Daems,
Antal van den Bosch,
Georges G. E. Gielen,
Willy M. C. Sansen:
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter.
DAC 2000: 452-457 |
| 26 | EE | Stephan Ohr,
Rob A. Rutenbar,
Henry Chang,
Georges G. E. Gielen,
Rudolf Koch,
Roy McGuffin,
K. C. Murphy:
Survival strategies for mixed-signal systems-on-chip (panel session).
DAC 2000: 579-580 |
| 25 | EE | Peter J. Vancorenland,
Carl De Ranter,
Michiel Steyaert,
Georges G. E. Gielen:
Optimal RF design using smart evolutionary algorithms.
DAC 2000: 7-10 |
| 24 | | Kenneth Francken,
Peter J. Vancorenland,
Georges G. E. Gielen:
DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators.
ICCAD 2000: 188-192 |
| 23 | | Erik Lauwers,
Georges G. E. Gielen:
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters.
ICCAD 2000: 193-196 |
| 1999 |
|---|
| 22 | EE | Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits.
DAC 1999: 958-963 |
| 21 | EE | Erik Lauwers,
Georges G. E. Gielen:
A Power Estimation Model for High-Speed CMOS A/D Converters.
DATE 1999: 401-405 |
| 20 | EE | Kenneth Francken,
Georges G. E. Gielen:
Methodology for analog technology porting including performance tuning.
ISCAS (1) 1999: 415-418 |
| 1998 |
|---|
| 19 | EE | Jan Vandenbussche,
Stéphane Donnay,
Francky Leyn,
Georges G. E. Gielen,
Willy M. C. Sansen:
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon.
DATE 1998: 716-720 |
| 18 | EE | Francky Leyn,
Georges G. E. Gielen,
Willy M. C. Sansen:
An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits.
ICCAD 1998: 304-307 |
| 17 | EE | Geert Debyser,
Georges G. E. Gielen:
Efficient analog circuit synthesis with simultaneous yield and robustness optimization.
ICCAD 1998: 308-311 |
| 16 | EE | Zhihua Wang,
Georges G. E. Gielen,
Willy M. C. Sansen:
Probabilistic fault detection and the selection of measurements for analog integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 862-872 (1998) |
| 1997 |
|---|
| 15 | EE | Stéphane Donnay,
Georges G. E. Gielen,
Willy M. C. Sansen,
Wim Kruiskamp,
Domine Leenaerts,
W. van Bokhoven:
High-level synthesis of analog sensor interface front-ends.
ED&TC 1997: 56-60 |
| 14 | EE | Francky Leyn,
Walter Daems,
Georges G. E. Gielen,
Willy M. C. Sansen:
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps.
ICCAD 1997: 374-381 |
| 13 | EE | Wim Verhaegen,
Geert Van der Plas,
Georges G. E. Gielen:
Automated test pattern generation for analog integrated circuits.
VTS 1997: 296-301 |
| 1996 |
|---|
| 12 | EE | L. Richard Carley,
Georges G. E. Gielen,
Rob A. Rutenbar,
Willy M. C. Sansen:
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.
DAC 1996: 298-303 |
| 1995 |
|---|
| 11 | EE | Koen Lampaert,
Georges G. E. Gielen,
Willy M. C. Sansen:
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits.
DAC 1995: 445-449 |
| 10 | EE | Jan Crols,
Stéphane Donnay,
Michiel Steyaert,
Georges G. E. Gielen:
A high-level design and optimization tool for analog RF receiver front-ends.
ICCAD 1995: 550-553 |
| 9 | | Georges G. E. Gielen,
Geert Debyser,
Piet Wambacq,
Koen Swings,
Willy M. C. Sansen:
Use of Symbolic Analysis in Analog Circuit Synthesis.
ISCAS 1995: 2205-2208 |
| 1994 |
|---|
| 8 | | Stéphane Donnay,
Koen Swings,
Georges G. E. Gielen,
Willy M. C. Sansen,
Wim Kruiskamp,
Domine Leenaerts:
A Methodology for Analog Design Automation in Mixed-Signal ASICs.
EDAC-ETC-EUROASIC 1994: 530-534 |
| 7 | EE | Georges G. E. Gielen,
Zhihua Wang,
Willy M. C. Sansen:
Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring.
ICCAD 1994: 495-498 |
| 6 | | Francisco V. Fernández,
Piet Wambacq,
Georges G. E. Gielen,
Ángel Rodríguez-Vázquez,
Willy M. C. Sansen:
Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation.
ISCAS 1994: 25-28 |
| 5 | | Zhihua Wang,
Georges G. E. Gielen,
Willy M. C. Sansen:
A Novel Method for the Fault Detection of Analog Integrated Circuits.
ISCAS 1994: 347-350 |
| 4 | | Francisco V. Fernández,
Georges G. E. Gielen,
Lawrence Huelsman,
Agnieszka Konczykowska,
Stefano Manetti,
Willy M. C. Sansen,
Jiri Vlach:
Pleasures, Perils and Pitfalls of Symbolic Analysis.
ISCAS 1994: 451-457 |
| 1993 |
|---|
| 3 | | Georges G. E. Gielen,
Willy M. C. Sansen:
Modeling of the Power-supply Interactions of CMOS Operational Amplifiers Using Symbolic Computation.
ISCAS 1993: 1381-1384 |
| 1991 |
|---|
| 2 | | Edward W. Y. Liu,
Alberto L. Sangiovanni-Vincentelli,
Georges G. E. Gielen,
Paul R. Gray:
A Behavioral Representation for Nyquist Rate A/D Converters.
ICCAD 1991: 386-389 |
| 1990 |
|---|
| 1 | EE | Georges G. E. Gielen,
Koen Swings,
Willy M. C. Sansen:
An intelligent design system for analogue integrated circuits.
EURO-DAC 1990: 169-173 |
