2009 |
30 | EE | Charles Augustine,
Arijit Raychowdhury,
Yunfei Gao,
Mark S. Lundstrom,
Kaushik Roy:
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.
ISQED 2009: 80-85 |
2008 |
29 | EE | Swarup Bhunia,
Hamid Mahmoodi,
Arijit Raychowdhury,
Kaushik Roy:
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.
J. Electronic Testing 24(6): 577-590 (2008) |
2006 |
28 | EE | Mark M. Budnik,
Arijit Raychowdhury,
Aditya Bansal,
Kaushik Roy:
A high density, carbon nanotube capacitor for decoupling applications.
DAC 2006: 935-938 |
27 | EE | Arijit Raychowdhury,
Bipul Chandra Paul,
Swarup Bhunia,
Kaushik Roy:
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
DATE 2006: 856-861 |
26 | EE | Swaroop Ghosh,
Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
IOLTS 2006: 31-36 |
25 | EE | Arijit Raychowdhury,
Xuanyao Fong,
Qikai Chen,
Kaushik Roy:
Analysis of super cut-off transistors for ultralow power digital logic circuits.
ISLPED 2006: 2-7 |
24 | EE | Amit Agarwal,
Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy,
Chris H. Kim:
Leakage Power Analysis and Reduction for Nanoscale Circuits.
IEEE Micro 26(2): 68-80 (2006) |
23 | EE | Nilanjan Banerjee,
Arijit Raychowdhury,
Kaushik Roy,
Swarup Bhunia,
Hamid Mahmoodi:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006) |
22 | EE | Arijit Raychowdhury,
Kaushik Roy:
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 58-65 (2006) |
21 | EE | Swaroop Ghosh,
Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006) |
2005 |
20 | EE | Saibal Mukhopadhyay,
Arijit Raychowdhury,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Asian Test Symposium 2005: 176-181 |
19 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Arijit Raychowdhury,
Kaushik Roy:
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
DATE 2005: 1136-1141 |
18 | EE | Nilanjan Banerjee,
Arijit Raychowdhury,
Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
ICCD 2005: 206-214 |
17 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
A Feasibility Study of Subthreshold SRAM Across Technology Generations.
ICCD 2005: 417-424 |
16 | EE | Arijit Raychowdhury,
Swaroop Ghosh,
Kaushik Roy:
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.
IOLTS 2005: 287-292 |
15 | EE | Arijit Raychowdhury,
Bipul Chandra Paul,
Swarup Bhunia,
Kaushik Roy:
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005) |
14 | EE | Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy:
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 363-381 (2005) |
13 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electronic Testing 21(2): 147-159 (2005) |
12 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electronic Testing 21(3): 243-255 (2005) |
2004 |
11 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.
DATE 2004: 704-705 |
10 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Arijit Raychowdhury,
Kaushik Roy:
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
DFT 2004: 314-315 |
9 | EE | Arijit Raychowdhury,
Kaushik Roy:
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.
ICCAD 2004: 237-240 |
8 | EE | Myeong-Eun Hwang,
Arijit Raychowdhury,
Kaushik Roy:
Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.
ISCAS (3) 2004: 709-712 |
7 | EE | Bipul Chandra Paul,
Arijit Raychowdhury,
Kaushik Roy:
Device optimization for ultra-low power digital sub-threshold operation.
ISLPED 2004: 96-101 |
6 | EE | Arijit Raychowdhury,
Kaushik Roy:
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.
ISMVL 2004: 14-19 |
5 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
ISQED 2004: 389-394 |
4 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
Modeling and Estimation of Leakage in Sub-90nm Devices.
VLSI Design 2004: 65- |
3 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
A circuit-compatible model of ballistic carbon nanotube field-effect transistors.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1411-1420 (2004) |
2003 |
2 | EE | Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy:
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
DAC 2003: 169-174 |
1 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
ICCAD 2003: 487-490 |