2009 |
61 | EE | María C. Molina,
Rafael Ruiz-Sautua,
Pedro Garcia-Repetto,
Román Hermida:
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 60-73 (2009) |
2008 |
60 | EE | Alberto A. Del Barrio,
María C. Molina,
Jose Manuel Mendias,
Esther Andres Perez,
Román Hermida,
Francisco Tirado:
Applying speculation techniques to implement functional units.
ICCD 2008: 74-80 |
2007 |
59 | EE | María C. Molina,
Rafael Ruiz-Sautua,
Jose Manuel Mendias,
Román Hermida:
Area optimization of multi-cycle operators in high-level synthesis.
DATE 2007: 449-454 |
58 | EE | David Atienza,
Pablo Garcia Del Valle,
Giacomo Paci,
Francesco Poletti,
Luca Benini,
Giovanni De Micheli,
Jose Manuel Mendias,
Román Hermida:
HW-SW emulation framework for temperature-aware design in MPSoCs.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
57 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
CoRR abs/0710.4801: (2007) |
2006 |
56 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Pre-synthesis optimization of multiplications to improve circuit performance.
DATE 2006: 1306-1311 |
55 | EE | Fredy Rivera,
Marcos Sanchez-Elez,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh:
Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.
FPL 2006: 1-8 |
54 | EE | José Luis Imaña,
Román Hermida,
Francisco Tirado:
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
IEEE Trans. VLSI Syst. 14(12): 1388-1393 (2006) |
53 | EE | María C. Molina,
Rafael Ruiz-Sautua,
Jose Manuel Mendias,
Román Hermida:
Bitwise scheduling to balance the computational cost of behavioral specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 31-46 (2006) |
2005 |
52 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Arrival time aware scheduling to minimize clock cycle length.
ASP-DAC 2005: 1018-1021 |
51 | EE | Rafael Ruiz-Sautua,
María C. Molina,
José M. Mendías,
Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.
DATE 2005: 1252-1257 |
50 | EE | Nicolas Genko,
David Atienza,
Giovanni De Micheli,
Jose Manuel Mendias,
Román Hermida,
Francky Catthoor:
A Complete Network-On-Chip Emulation Framework.
DATE 2005: 246-251 |
49 | | Rafael Ruiz-Sautua,
María C. Molina,
Jose Manuel Mendias,
Román Hermida:
Performance-driven read-after-write dependencies softening in high-level synthesis.
ICCAD 2005: 7-12 |
48 | EE | Fredy Rivera,
Marcos Sanchez-Elez,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh:
Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures.
IPDPS 2005 |
47 | EE | Nicolas Genko,
David Atienza,
Giovanni De Micheli,
Luca Benini,
Jose Manuel Mendias,
Román Hermida,
Francky Catthoor:
A novel approach for network on chip emulation.
ISCAS (3) 2005: 2365-2368 |
46 | | J. B. Pérez-Ramas,
David Atienza,
M. Peón,
Ivan Magan,
Jose Manuel Mendias,
Román Hermida:
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
PARCO 2005: 769-776 |
2004 |
45 | EE | Fredy Rivera,
Marcos Sanchez-Elez,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh:
Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures.
CODES+ISSS 2004: 30-35 |
44 | EE | María C. Molina,
Rafael Ruiz-Sautua,
José M. Mendías,
Román Hermida:
Behavioural Bitwise Scheduling Based on Computational Effort Balancing.
DATE 2004: 684-685 |
43 | EE | María C. Molina,
Rafael Ruiz-Sautua,
José M. Mendías,
Román Hermida:
Behavioural Scheduling to Balance the Bit-Level Computational Effort.
ISVLSI 2004: 99-104 |
42 | EE | José Manuel Colmenar,
Oscar Garnica,
Sonia López,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.
PDP 2004: 112-119 |
41 | EE | Juan de Vicente,
Juan Lanchares,
Román Hermida:
Annealing placement by thermodynamic combinatorial optimization.
ACM Trans. Design Autom. Electr. Syst. 9(3): 310-332 (2004) |
2003 |
40 | EE | Marcos Sanchez-Elez,
Milagros Fernández,
Manuel L. Anido,
Haitao Du,
Nader Bagherzadeh,
Román Hermida:
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.
DATE 2003: 10036-10043 |
39 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage.
DATE 2003: 10264-10269 |
38 | EE | José Ignacio Hidalgo,
Francisco Fernández de Vega,
Juan Lanchares,
Juan Manuel Sánchez-Pérez,
Román Hermida,
Marco Tomassini,
Ranieri Baraglia,
Raffaele Perego,
Oscar Garnica:
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation.
GECCO 2003: 2109-2120 |
37 | EE | Sonia López,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
PATMOS 2003: 151-160 |
36 | EE | María C. Molina,
Rafael Ruiz-Sautua,
José M. Mendías,
Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
PATMOS 2003: 617-627 |
35 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources.
Journal of Systems Architecture 49(12-15): 505-519 (2003) |
2002 |
34 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
High-level synthesis of multiple-precision circuitsindependent of data-objects length.
DAC 2002: 612-615 |
33 | EE | Olga Peñalba,
José M. Mendías,
Román Hermida:
Maximizing Conditonal Reuse by Pre-Synthesis Transformations.
DATE 2002: 1097 |
32 | EE | Juan de Vicente,
Juan Lanchares,
Román Hermida:
FPGA Placement by Thermodynamic Combinatorial Optimization.
DATE 2002: 54-60 |
31 | EE | Marcos Sanchez-Elez,
Milagros Fernández,
Rafael Maestre,
Rafael Maestre,
Fadi J. Kurdahi,
Román Hermida,
Nader Bagherzadeh:
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.
DATE 2002: 547-552 |
30 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Multiple-Precision Circuits Allocation Independent of Data-Objects Length.
DATE 2002: 909-915 |
29 | EE | Aitor Ibarra,
José M. Mendías,
Juan Lanchares,
José Ignacio Hidalgo,
Román Hermida:
Optimization of Equational Specifications Using Genetic Techniques.
DSD 2002: 252-258 |
28 | EE | José M. Mendías,
Román Hermida,
María C. Molina,
Olga Peñalba:
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.
DSD 2002: 308-315 |
27 | EE | Olga Peñalba,
José M. Mendías,
Román Hermida:
Source Code Transformation to Improve Conditional Hardware Reuse.
DSD 2002: 324-331 |
26 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Bit-Level Allocation of Multiple-Precision Specifications.
DSD 2002: 385-392 |
25 | EE | José Ignacio Hidalgo,
Juan Lanchares,
Aitor Ibarra,
Román Hermida:
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design.
DSD 2002: 60-69 |
24 | EE | Aitor Ibarra,
Juan Lanchares,
Jose Manuel Mendias,
José Ignacio Hidalgo,
Román Hermida:
Transformation of Equational Specification by Means of Genetic Programming.
EuroGP 2002: 248-257 |
23 | EE | María C. Molina,
José M. Mendías,
Román Hermida:
Bit-level scheduling of heterogeneous behavioural specifications.
ICCAD 2002: 602-608 |
22 | EE | Oscar Garnica,
Juan Lanchares,
Román Hermida:
A New Methodology to Design Low-Power Asynchronous Circuits.
PATMOS 2002: 108-117 |
21 | | Oscar Garnica,
Juan Lanchares,
Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.
Fundam. Inform. 50(2): 155-174 (2002) |
20 | EE | José M. Mendías,
Román Hermida,
Olga Peñalba:
A study about the efficiency of formal high-level synthesis applied to verification.
Integration 31(2): 101-131 (2002) |
2001 |
19 | EE | Oscar Garnica,
Juan Lanchares,
Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.
ACSD 2001: 167-178 |
18 | EE | Oscar Garnica,
Juan Lanchares,
Román Hermida:
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.
DATE 2001: 810 |
17 | | Marcos Sanchez-Elez,
Milagros Fernández,
Román Hermida,
Rafael Maestre,
Fadi J. Kurdahi,
Nader Bagherzadeh:
A data scheduler for multi-context reconfigurable architectures.
ISSS 2001: 177-182 |
16 | EE | Rafael Maestre,
F. Kurdahl,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh,
Hartej Singh:
A formal approach to context scheduling for multicontext reconfigurable architectures.
IEEE Trans. VLSI Syst. 9(1): 173-185 (2001) |
15 | EE | Rafael Maestre,
Fadi J. Kurdahi,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh,
Hartej Singh:
A framework for reconfigurable computing: task scheduling and context management.
IEEE Trans. VLSI Syst. 9(6): 858-873 (2001) |
2000 |
14 | EE | José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms.
EUROMICRO 2000: 1204-1211 |
13 | EE | Rafael Maestre,
Milagros Fernández,
Román Hermida,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
FCCM 2000: 297-298 |
12 | EE | Rafael Maestre,
Milagros Fernández,
Román Hermida,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
ICCD 2000: 575-576 |
11 | EE | Juan de Vicente,
Juan Lanchares,
Román Hermida:
Adaptive FPGA Placement by Natural Optimization.
IEEE International Workshop on Rapid System Prototyping 2000: 188-193 |
1999 |
10 | EE | J. A. Maestro,
Daniel Mozos,
Román Hermida:
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.
DATE 1999: 766-767 |
9 | EE | Rafael Maestre,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Hartej Singh,
Román Hermida,
Milagros Fernández:
Kernel Scheduling in Reconfigurable Computing.
DATE 1999: 90-96 |
8 | EE | Olga Peñalba,
José M. Mendías,
Román Hermida:
A Unified Algorithm for Mutual Exclusiveness Identification.
EUROMICRO 1999: 1504-1510 |
7 | | Juan de Vicente,
Juan Lanchares,
Román Hermida:
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies.
FPL 1999: 91-100 |
6 | EE | Rafael Maestre,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh:
A Framework for Scheduling and Context Allocation in Reconfigurable Computing.
ISSS 1999: 134-140 |
1998 |
5 | EE | José M. Mendías,
Román Hermida:
Correct High-Level Synthesis: a Formal Perspective.
DATE 1998: 977-978 |
4 | EE | Juan de Vicente,
Juan Lanchares,
Román Hermida:
RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing.
EUROMICRO 1998: 10192-10195 |
1997 |
3 | EE | José M. Mendías,
Román Hermida,
Milagros Fernández:
Formal Techniques for Hardware Allocation.
VLSI Design 1997: 161-165 |
2 | EE | R. Moreno,
Román Hermida,
Milagros Fernández,
Hortensia Mecha:
A unified approach for scheduling and allocation.
Integration 23(1): 1-35 (1997) |
1996 |
1 | EE | R. Moreno,
Román Hermida,
Milagros Fernández:
Register estimation in unscheduled dataflow graphs.
ACM Trans. Design Autom. Electr. Syst. 1(3): 396-403 (1996) |