| 2009 |
|---|
| 139 | EE | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Defect Aware to Power Conscious Tests - The New DFT Landscape.
VLSI Design 2009: 23-25 |
| 138 | EE | Nilanjan Mukherjee,
Artur Pogiel,
Janusz Rajski,
Jerzy Tyszer:
High-Speed On-Chip Event Counters for Embedded Systems.
VLSI Design 2009: 275-280 |
| 137 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 245-258 (2009) |
| 2008 |
|---|
| 136 | EE | Santiago Remersaro,
Janusz Rajski,
Thomas Rinderknecht,
Sudhakar M. Reddy,
Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
DFT 2008: 385-393 |
| 135 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis.
ISQED 2008: 246-253 |
| 134 | EE | Janusz Rajski,
Jerzy Tyszer,
Grzegorz Mrugalski,
Wu-Tung Cheng,
Neelanjan Mukherjee,
Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008) |
| 133 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 932-945 (2008) |
| 132 | EE | Dariusz Czysz,
Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1278-1290 (2008) |
| 2007 |
|---|
| 131 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Dariusz Czysz,
Jerzy Tyszer:
New Test Data Decompressor for Low Power Applications.
DAC 2007: 539-544 |
| 130 | EE | Dhiraj Goswami,
Kun-Han Tsai,
Mark Kassab,
Janusz Rajski:
Test Generation in the Presence of Timing Exceptions and Constraints.
DAC 2007: 688-693 |
| 129 | | Janusz Rajski:
Logic Diagnosis and Yield Learning.
DDECS 2007: 19 |
| 128 | EE | Huaxing Tang,
Manish Sharma,
Janusz Rajski,
Martin Keim,
Brady Benware:
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement.
European Test Symposium 2007: 145-150 |
| 127 | EE | Santiago Remersaro,
Xijiang Lin,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
Low Shift and Capture Power Scan Tests.
VLSI Design 2007: 793-798 |
| 126 | EE | Chris Schuermyer,
Jewel Pangilinan,
Jay Jahangiri,
Martin Keim,
Janusz Rajski,
Brady Benware:
Silicon Evaluation of Static Alternative Fault Models.
VTS 2007: 265-270 |
| 125 | EE | Dariusz Czysz,
Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Low Power Embedded Deterministic Test.
VTS 2007: 75-83 |
| 124 | EE | Santiago Remersaro,
Xijiang Lin,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
Scan-Based Tests with Low Switching Activity.
IEEE Design & Test of Computers 24(3): 268-275 (2007) |
| 123 | EE | Jerzy Tyszer,
Janusz Rajski,
Grzegorz Mrugalski,
Nilanjan Mukherjee,
Mark Kassab,
Wu-Tung Cheng,
Manish Sharma,
Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.
IEEE Design & Test of Computers 24(5): 476-485 (2007) |
| 122 | EE | Grzegorz Mrugalski,
Artur Pogiel,
Janusz Rajski,
Jerzy Tyszer:
Fault Diagnosis With Convolutional Compactors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1478-1494 (2007) |
| 121 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Chen Wang,
Artur Pogiel,
Jerzy Tyszer:
Isolation of Failing Scan Cells through Convolutional Test Response Compaction.
J. Electronic Testing 23(1): 35-45 (2007) |
| 2006 |
|---|
| 120 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Test response compactor with programmable selector.
DAC 2006: 1089-1094 |
| 119 | EE | Gang Chen,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
A test pattern ordering algorithm for diagnosis with truncated fail data.
DAC 2006: 399-404 |
| 118 | EE | Artur Pogiel,
Janusz Rajski,
Jerzy Tyszer:
Convolutional Compactors with Variable Polynomials.
European Test Symposium 2006: 117-122 |
| 117 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski,
Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan.
European Test Symposium 2006: 21-28 |
| 116 | EE | Vishal J. Mehta,
Malgorzata Marek-Sadowska,
Zhiyuan Wang,
Kun-Han Tsai,
Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test.
ISQED 2006: 463-472 |
| 115 | EE | Gang Chen,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.
VLSI Design 2006: 419-424 |
| 114 | EE | Xijiang Lin,
Janusz Rajski:
The Impacts of Untestable Defects on Transition Fault Testing.
VTS 2006: 2-7 |
| 113 | EE | Wojciech Rajski,
Janusz Rajski:
Modular Compactor of Test Responses.
VTS 2006: 242-251 |
| 112 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz,
Xijiang Lin,
Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults.
VTS 2006: 343-348 |
| 111 | EE | Grzegorz Mrugalski,
Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
High Performance Dense Ring Generators.
IEEE Trans. Computers 55(1): 83-87 (2006) |
| 110 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 558-575 (2006) |
| 2005 |
|---|
| 109 | EE | Xijiang Lin,
Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults.
ASP-DAC 2005: 178-183 |
| 108 | EE | Janusz Rajski:
Embedded Test Technology - Brief History, Current Status, and Future Directions.
Asian Test Symposium 2005 |
| 107 | EE | Huaxing Tang,
Gang Chen,
Sudhakar M. Reddy,
Chen Wang,
Janusz Rajski,
Irith Pomeranz:
Defect Aware Test Patterns.
DATE 2005: 450-455 |
| 106 | EE | Huaxing Tang,
Chen Wang,
Janusz Rajski,
Sudhakar M. Reddy,
Jerzy Tyszer,
Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
VLSI Design 2005: 59-64 |
| 105 | EE | Janusz Rajski,
Jerzy Tyszer:
Synthesis of X-Tolerant Convolutional Compactors.
VTS 2005: 114-119 |
| 104 | EE | Janusz Rajski,
Jerzy Tyszer,
Chen Wang,
Sudhakar M. Reddy:
Finite memory test response compactors for embedded test applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 622-634 (2005) |
| 103 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Delay-fault diagnosis using timing information.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1315-1325 (2005) |
| 2004 |
|---|
| 102 | EE | Wu-Tung Cheng,
Kun-Han Tsai,
Yu Huang,
Nagesh Tamarapalli,
Janusz Rajski:
Compactor Independent Direct Diagnosis.
Asian Test Symposium 2004: 204-209 |
| 101 | EE | Janusz Rajski,
Kan Thapar:
Nanometer Design: What are the Requirements for Manufacturing Test?
DATE 2004: 930-937 |
| 100 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Diagnosis of Hold Time Defects.
ICCD 2004: 192-199 |
| 99 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Delay Fault Diagnosis Using Timing Information.
ISQED 2004: 485-490 |
| 98 | EE | Brady Benware,
Cam Lu,
John Van Slyke,
Prabhu Krishnamurthy,
Robert Madge,
Martin Keim,
Mark Kassab,
Janusz Rajski:
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.
ITC 2004: 1285-1294 |
| 97 | EE | Grzegorz Mrugalski,
Chen Wang,
Artur Pogiel,
Jerzy Tyszer,
Janusz Rajski:
Fault Diagnosis in Designs with Convolutional Compactors.
ITC 2004: 498-507 |
| 96 | EE | Xinli Gu,
Cyndee Wang,
Abby Lee,
Bill Eklow,
Kun-Han Tsai,
Jan Arild Tofte,
Mark Kassab,
Janusz Rajski:
Realizing High Test Quality Goals with Smart Test Resource Usage.
ITC 2004: 525-533 |
| 95 | EE | Janusz Rajski,
Nilanjan Mukherjee,
Jerzy Tyszer,
Thomas Rinderknecht:
Embedded Test for Low Cost Manufacturing.
VLSI Design 2004: 21-23 |
| 94 | EE | Grzegorz Mrugalski,
Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Planar High Performance Ring Generators.
VTS 2004: 193-198 |
| 93 | EE | Janusz Rajski,
Jerzy Tyszer,
Mark Kassab,
Nilanjan Mukherjee:
Embedded deterministic test.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004) |
| 92 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Ring generators - new devices for embedded test applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1306-1320 (2004) |
| 2003 |
|---|
| 91 | EE | Chen Wang,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski,
Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values.
ICCAD 2003: 855-862 |
| 90 | EE | Zhiyuan Wang,
Malgorzata Marek-Sadowska,
Kun-Han Tsai,
Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests.
ICCD 2003: 198- |
| 89 | EE | Janusz Rajski,
Jerzy Tyszer:
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs.
ICCD 2003: 331- |
| 88 | EE | Brady Benware,
Chris Schuermyer,
Sreenevasan Ranganathan,
Robert Madge,
Prabhu Krishnamurthy,
Nagesh Tamarapalli,
Kun-Han Tsai,
Janusz Rajski:
Impact of Multiple-Detect Test Patterns on Product Quality.
ITC 2003: 1031-1040 |
| 87 | EE | Frank Poehl,
Matthias Beck,
Ralf Arnold,
Peter Muhmenthaler,
Nagesh Tamarapalli,
Mark Kassab,
Nilanjan Mukherjee,
Janusz Rajski:
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
ITC 2003: 1211-1220 |
| 86 | EE | Janusz Rajski:
Test Challenges of Nanometer Technology.
ITC 2003: 13-22 |
| 85 | EE | Zhiyuan Wang,
Kun-Han Tsai,
Malgorzata Marek-Sadowska,
Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis.
ITC 2003: 329-338 |
| 84 | EE | Janusz Rajski,
Jerzy Tyszer,
Chen Wang,
Sudhakar M. Reddy:
Convolutional Compaction of Test Responses.
ITC 2003: 745-754 |
| 83 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
High Speed Ring Generators and Compactors of Test Data.
VTS 2003: 57-62 |
| 82 | EE | Grzegorz Mrugalski,
Jerzy Tyszer,
Janusz Rajski:
2D Test Sequence Generators.
IEEE Design & Test of Computers 20(1): 51-59 (2003) |
| 81 | EE | Xijiang Lin,
Ron Press,
Janusz Rajski,
Paul Reuter,
Thomas Rinderknecht,
Bruce Swanson,
Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing.
IEEE Design & Test of Computers 20(5): 17-25 (2003) |
| 80 | EE | Janusz Rajski,
Mark Kassab,
Nilanjan Mukherjee,
Nagesh Tamarapalli,
Jerzy Tyszer,
Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing.
IEEE Design & Test of Computers 20(5): 58-66 (2003) |
| 79 | EE | Janusz Rajski,
Jerzy Tyszer:
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients.
J. Electronic Testing 19(6): 645-657 (2003) |
| 2002 |
|---|
| 78 | EE | Irith Pomeranz,
Janusz Rajski,
Sudhakar M. Reddy:
Finding a Common Fault Response for Diagnosis during Silicon Debug.
DATE 2002: 1116 |
| 77 | EE | Chen Wang,
Sudhakar M. Reddy,
Irith Pomeranz,
Xijiang Lin,
Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation.
ICCAD 2002: 87-93 |
| 76 | EE | Janusz Rajski,
Jerzy Tyszer,
Mark Kassab,
Nilanjan Mukherjee,
Rob Thompson,
Kun-Han Tsai,
Andre Hertwig,
Nagesh Tamarapalli,
Grzegorz Mrugalski,
Geir Eide,
Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test.
ITC 2002: 301-310 |
| 75 | EE | Nadir Z. Basturkmen,
Sudhakar M. Reddy,
Janusz Rajski:
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST.
VLSI Design 2002: 604- |
| 74 | EE | J. Borel,
Anand Raghunathan,
Jim Sproch,
Michael Howells,
Janusz Rajski:
Innovations in Test Automation.
VTS 2002: 43-46 |
| 2001 |
|---|
| 73 | EE | Janusz Rajski:
DFT for High-Quality Low Cost Manufacturing Test.
Asian Test Symposium 2001: 3- |
| 72 | | Xijiang Lin,
Janusz Rajski,
Irith Pomeranz,
Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs.
ITC 2001: 1088-1097 |
| 71 | | John T. Chen,
Jitendra Khare,
Ken Walker,
Saghir A. Shaikh,
Janusz Rajski,
Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
ITC 2001: 258-267 |
| 70 | EE | John T. Chen,
Wojciech Maly,
Janusz Rajski,
Omar Kebichi,
Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression.
VTS 2001: 292-298 |
| 69 | EE | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Testing Schemes for FIR Filter Structures.
IEEE Trans. Computers 50(7): 674-688 (2001) |
| 2000 |
|---|
| 68 | EE | Xiaoliang Bai,
Sujit Dey,
Janusz Rajski:
Self-test methodology for at-speed test of crosstalk in chip interconnects.
DAC 2000: 619-624 |
| 67 | | Yu Huang,
Irith Pomeranz,
Sudhakar M. Reddy,
Janusz Rajski:
Improving the Proportion of At-Speed Tests in Scan BIST.
ICCAD 2000: 459-463 |
| 66 | EE | Grzegorz Mrugalski,
Jerzy Tyszer,
Janusz Rajski:
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators.
VTS 2000: 377-388 |
| 65 | EE | Janusz Rajski,
Nagesh Tamarapalli,
Jerzy Tyszer:
Automated synthesis of phase shifters for built-in self-testapplications.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1175-1188 (2000) |
| 64 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Cellular automata-based test pattern generators with phase shifters.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 878-893 (2000) |
| 63 | EE | Kun-Han Tsai,
Janusz Rajski,
Malgorzata Marek-Sadowska:
Star test: the theory and its applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1052-1064 (2000) |
| 1999 |
|---|
| 62 | | Kuo-Hui Tsai,
Tompson,
Janusz Rajski,
Malgorzata Marek-Sadowska:
STAR-ATPG: a high speed test pattern generator for large scan designs.
ITC 1999: 1021-1030 |
| 61 | | Graham Hetherington,
Tony Fryars,
Nagesh Tamarapalli,
Mark Kassab,
Abu S. M. Hassan,
Janusz Rajski:
Logic BIST for large industrial designs: real issues and case studies.
ITC 1999: 358-367 |
| 60 | | Grzegorz Mrugalski,
Jerzy Tyszer,
Janusz Rajski:
Synthesis of pattern generators based on cellular automata with phase shifters.
ITC 1999: 368-377 |
| 59 | | Janusz Rajski,
Jerzy Tyszer,
Sanjay Patel:
Built-In Self-Test for Systems on Silicon.
VLSI Design 1999: 609-610 |
| 58 | EE | Janusz Rajski,
Grzegorz Mrugalski,
Jerzy Tyszer:
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters.
VTS 1999: 236-245 |
| 57 | | Janusz Rajski,
Jerzy Tyszer:
Diagnosis of Scan Cells in BIST Environment.
IEEE Trans. Computers 48(7): 724-731 (1999) |
| 1998 |
|---|
| 56 | EE | Aiman H. El-Maleh,
Mark Kassab,
Janusz Rajski:
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.
DAC 1998: 625-631 |
| 55 | EE | Janusz Rajski,
Nagesh Tamarapalli,
Jerzy Tyszer:
Automated synthesis of large phase shifters for built-in self-test.
ITC 1998: 1047-1056 |
| 54 | EE | Janusz Rajski,
Jerzy Tyszer:
Modular logic built-in self-test for IP cores.
ITC 1998: 313- |
| 53 | EE | Janusz Rajski,
Jerzy Tyszer:
Design of Phase Shifters for BIST Applications.
VTS 1998: 218-224 |
| 52 | | Janusz Rajski,
Jerzy Tyszer,
Nadime Zacharia:
Test Data Decompression for Multiple Scan Designs with Boundary Scan.
IEEE Trans. Computers 47(11): 1188-1200 (1998) |
| 1997 |
|---|
| 51 | EE | Kun-Han Tsai,
Sybille Hellebrand,
Janusz Rajski,
Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation.
DAC 1997: 472-477 |
| 50 | | Kun-Han Tsai,
Malgorzata Marek-Sadowska,
Janusz Rajski:
Scan-Encoded Test Pattern Generation for BIST.
ITC 1997: 548-556 |
| 49 | | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Parameterizable Testing Scheme for FIR Filters.
ITC 1997: 694-703 |
| 48 | | Janusz Rajski,
Jerzy Tyszer:
Fault Diagnosis in Scan-Based BIST.
ITC 1997: 894-902 |
| 47 | EE | J. Borel,
M. Cecchini,
C. Malipeddi,
Janusz Rajski,
Yervant Zorian:
Systems On Silicon: Design and Test Challenges.
VTS 1997: 184-185 |
| 46 | | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Design of Testable Multipliers for Fixed-Width Data Paths.
IEEE Trans. Computers 46(7): 795-810 (1997) |
| 45 | EE | Katarzyna Radecka,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1358-1369 (1997) |
| 44 | EE | Aiman H. El-Maleh,
Thomas E. Marchok,
Janusz Rajski,
Wojciech Maly:
Behavior and testability preservation under the retiming transformation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 528-543 (1997) |
| 1996 |
|---|
| 43 | | Nadime Zacharia,
Janusz Rajski,
Jerzy Tyszer,
John A. Waicukauski:
Two-Dimensional Test Data Decompressor for Multiple Scan Designs.
ITC 1996: 186-194 |
| 42 | | Nagesh Tamarapalli,
Janusz Rajski:
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST.
ITC 1996: 649-658 |
| 41 | EE | Fidel Muradali,
Janusz Rajski:
A self-driven test structure for pseudorandom testing of non-scan sequential circuits.
VTS 1996: 17-25 |
| 40 | EE | J. El-Ziq,
Najmi T. Jarwala,
Niraj K. Jha,
Peter Marwedel,
Christos A. Papachristou,
Janusz Rajski,
John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw!
VTS 1996: 506-507 |
| 39 | | Janusz Rajski,
Jerzy Tyszer:
On Linear Dependencies in Subspaces of LFSR-Generated Sequences.
IEEE Trans. Computers 45(10): 1212-1216 (1996) |
| 38 | | Sanjay Gupta,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns.
IEEE Trans. Computers 45(8): 939-949 (1996) |
| 37 | EE | Thomas E. Marchok,
Aiman H. El-Maleh,
Wojciech Maly,
Janusz Rajski:
A complexity analysis of sequential ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1409-1423 (1996) |
| 1995 |
|---|
| 36 | EE | Aiman H. El-Maleh,
Thomas E. Marchok,
Janusz Rajski,
Wojciech Maly:
On Test Set Preservation of Retimed Circuits.
DAC 1995: 176-182 |
| 35 | EE | Mark Kassab,
Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Software Accelerated Functional Fault Simulation for Data-Path Architectures.
DAC 1995: 333-338 |
| 34 | EE | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
On testable multipliers for fixed-width data path architectures.
ICCAD 1995: 541-547 |
| 33 | | Mark Kassab,
Janusz Rajski,
Jerzy Tyszer:
Hierarchical Functional-Fault Simulation for High-Level Synthesis.
ITC 1995: 596-605 |
| 32 | EE | Nilanjan Mukherjee,
H. Kassab,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic built-in self test for high-level synthesis.
VTS 1995: 132-139 |
| 31 | EE | Marc Riedel,
Janusz Rajski:
Fault coverage analysis of RAM test algorithms.
VTS 1995: 227-234 |
| 30 | EE | Nadime Zacharia,
Janusz Rajski,
Jerzy Tyszer:
Decompression of test data using variable-length seed LFSRs.
VTS 1995: 426-433 |
| 29 | EE | Thomas E. Marchok,
Aiman H. El-Maleh,
Janusz Rajski,
Wojciech Maly:
Testability Implications of Performance-Driven Logic Synthesis.
IEEE Design & Test of Computers 12(2): 32-39 (1995) |
| 28 | | Sybille Hellebrand,
Janusz Rajski,
Steffen Tarnick,
Srikanth Venkataraman,
Bernard Courtois:
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.
IEEE Trans. Computers 44(2): 223-233 (1995) |
| 27 | EE | Aiman H. El-Maleh,
Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 582-590 (1995) |
| 1994 |
|---|
| 26 | EE | Sanjay Gupta,
Janusz Rajski,
Jerzy Tyszer:
Test pattern generation based on arithmetic operations.
ICCAD 1994: 117-124 |
| 25 | EE | Henry Cox,
Janusz Rajski:
On necessary and nonconflicting assignments in algorithmic test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 515-530 (1994) |
| 1993 |
|---|
| 24 | | Janusz Rajski,
Jerzy Tyszer:
Recursive Pseudoexhaustive Test Pattern Generation.
IEEE Trans. Computers 42(12): 1517-1521 (1993) |
| 23 | | Janusz Rajski,
Jerzy Tyszer:
Accumulator-Based Compaction of Test Responses.
IEEE Trans. Computers 42(6): 643-650 (1993) |
| 22 | EE | Fadi Maamari,
Janusz Rajski:
The dynamic reduction of fault simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 137-148 (1993) |
| 21 | EE | Janusz Rajski,
Jerzy Tyszer:
Test responses compaction in accumulators with rotate carry adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 531-539 (1993) |
| 1992 |
|---|
| 20 | | Sybille Hellebrand,
Steffen Tarnick,
Bernard Courtois,
Janusz Rajski:
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.
ITC 1992: 120-129 |
| 19 | EE | Ashish Pancholy,
Janusz Rajski,
Larry J. McNaughton:
Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits.
IEEE Design & Test of Computers 9(1): 72-83 (1992) |
| 18 | EE | Abu S. M. Hassan,
Vinod K. Agarwal,
Benoit Nadeau-Dostie,
Janusz Rajski:
BIST of PCB interconnects using boundary-scan architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1278-1288 (1992) |
| 17 | EE | Janusz Rajski,
Jagadeesh Vasudevamurthy:
The testability-preserving concurrent decomposition and factorization of Boolean expressions.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 778-793 (1992) |
| 1991 |
|---|
| 16 | EE | Stephen Pateras,
Janusz Rajski:
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits.
DAC 1991: 347-352 |
| 15 | | Stephen Pateras,
Janusz Rajski:
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits.
ITC 1991: 473-482 |
| 14 | EE | Janusz Rajski,
Jerzy Tyszer:
On the diagnostic properties of linear feedback shift registers.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(10): 1316-1322 (1991) |
| 1990 |
|---|
| 13 | | Janusz Rajski,
Jerzy Tyszer,
Babak Salimi:
On the Diagnostic Resolution of Signature Analysis.
ICCAD 1990: 364-367 |
| 12 | | Jagadeesh Vasudevamurthy,
Janusz Rajski:
A Method for Concurrent Decomposition and Factorization of Boolean Expressions.
ICCAD 1990: 510-513 |
| 11 | EE | Fadi Maamari,
Janusz Rajski:
A method of fault simulation based on stem regions.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 212-220 (1990) |
| 1989 |
|---|
| 10 | | Abu S. M. Hassan,
Vinod K. Agarwal,
Janusz Rajski,
Benoit Nadeau-Dostie:
Testing of Glue Logic Interconnects Using Boundary Scan Architecture.
ITC 1989: 700-711 |
| 1988 |
|---|
| 9 | | Abu S. M. Hassan,
Vinod K. Agarwal,
Janusz Rajski:
Testing and Diagnosis of Interconnects Using Boundary Scan Architecture.
ITC 1988: 126-137 |
| 8 | | Henry Cox,
André Ivanov,
Vinod K. Agarwal,
Janusz Rajski:
On Multiple Fault Coverage and Aliasing Probability Measures.
ITC 1988: 314-321 |
| 7 | | Henry Cox,
Janusz Rajski:
Stuck-Open and Transition Fault Testing in CMOS Complex Gates.
ITC 1988: 688-694 |
| 6 | | Markus Robinson,
Janusz Rajski:
An Algorithmic Branch and Bound Method for PLA Test Pattern Generation.
ITC 1988: 784-795 |
| 5 | EE | Henry Cox,
Janusz Rajski:
A method of fault analysis for test generation and fault diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(7): 813-833 (1988) |
| 1986 |
|---|
| 4 | | Janusz Rajski,
Jerzy Tyszer:
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's.
IEEE Trans. Computers 35(1): 81-85 (1986) |
| 1985 |
|---|
| 3 | | Vinod K. Agarwal,
Janusz Rajski:
Testing Properties and Applications of Inverter-Free PLA's.
ITC 1985: 500-507 |
| 2 | | Janusz Rajski,
Jerzy Tyszer:
Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays.
IEEE Trans. Computers 34(6): 549-553 (1985) |
| 1984 |
|---|
| 1 | | Janusz Rajski,
Jerzy Tyszer:
The detection of small size multiple faults by single fault test sets n programmable logic arrays.
Fehlertolerierende Rechensysteme 1984: 417-425 |
