| 2007 |
|---|
| 9 | EE | Tobias Bjerregaard,
Mikkel Bystrup Stensgaard,
Jens Sparsø:
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.
DATE 2007: 648-653 |
| 2006 |
|---|
| 8 | EE | Mikkel Bystrup Stensgaard,
Tobias Bjerregaard,
Jens Sparsø,
Johnny Halkjær Pedersen:
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.
DSD 2006: 641-648 |
| 7 | EE | Tobias Bjerregaard,
Jens Sparsø:
Packetizing OCP Transactions in the MANGO Network-on-Chip.
DSD 2006: 657-664 |
| 6 | EE | Tobias Bjerregaard,
Shankar Mahadevan:
A survey of research and practices of Network-on-chip.
ACM Comput. Surv. 38(1): (2006) |
| 5 | EE | Girish Venkataramani,
Tobias Bjerregaard,
Tiberiu Chelcea,
Seth Copen Goldstein:
Hardware compilation of application-specific memory-access interconnect.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 756-771 (2006) |
| 2005 |
|---|
| 4 | EE | Tobias Bjerregaard,
Jens Sparsø:
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip.
ASYNC 2005: 34-43 |
| 3 | EE | Girish Venkataramani,
Tiberiu Chelcea,
Seth Copen Goldstein,
Tobias Bjerregaard:
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.
CODES+ISSS 2005: 231-236 |
| 2 | EE | Tobias Bjerregaard,
Jens Sparsø:
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip.
DATE 2005: 1226-1231 |
| 2004 |
|---|
| 1 | EE | Tobias Bjerregaard,
Shankar Mahadevan,
Jens Sparsø:
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.
PATMOS 2004: 301-310 |
